Proceedings of 2011 6th International Forum on Strategic Technology 2011
DOI: 10.1109/ifost.2011.6021107
|View full text |Cite
|
Sign up to set email alerts
|

On a gate sizing of multiple-paths circuit for optimizing power-delay

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
0
0

Publication Types

Select...

Relationship

0
0

Authors

Journals

citations
Cited by 0 publications
references
References 5 publications
0
0
0
Order By: Relevance

No citations

Set email alert for when this publication receives citations?