On Aging-Aware Signoff for Circuits With Adaptive Voltage Scaling

Chan, Theodore; Chan, Wei-Ting Jonas; Kahng, Andrew B.

doi:10.1109/tcsi.2014.2321204

Cited by 10 publications

(5 citation statements)

References 22 publications

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“…In academia, there are a few analytical approaches to reflect and estimate PVT variations [25]- [28]. While these variation models claim accurate estimation results, they do not cover all of the process, voltage, and temperature variations; these models typically target specific physical aspects of devices.…”

Section: Cross-corner Variation Modelsmentioning

confidence: 99%

Cross-Corner Delay Variation Model for Standard Cell Libraries

Kim

Joo²,

Park

et al. 2021

IEEE Access

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For timing closure of logic circuits, circuit designers must perform sign-offs on a variety of process, voltage, and temperature (PVT) conditions. Designs of advanced logic circuits involve a multitude of voltage islands and operating modes, each of which requires delay characterizations at nearby PVT corners. Furthermore, advanced technologies nodes suffer from corner explosion: while the impact of PVT variations is being exacerbated, process variations are also diversifying, increasing the number of operating conditions exponentially. This paper revisits the importance of cross-corner timing estimations and proposes a delay variation model to mitigate such corner explosion. Our objective is to reduce PVT corner characterization effort for timely static timing analysis on an exploding number of operating conditions. Our proposed Decomposed Propagation Vector Variation Model (DPVVM) decomposes propagation delay and timing constraints into the driving by the receiver cell and its driver cell; by scaling them separately, delay characterization effort is reduced to a fraction of time while realizing accurate timing estimations. We also propose Multi-Dimension Recomposition (MDR) scheme, which exploits a multitude of pre-characterized corners to further improve the consistency of cross-corner timing estimations. As a result, with only 8.0% of a corner characterization effort compared to the full-characterization, DPVVM combined with MDR achieves overall cross-corner timing estimation errors of 4.8% and 5.6% for single cells and complex logic circuits-or improvements of 69% and 61% over the conventional derating method, respectively. Our proposed method's characterization overhead is 11% over the conventional derating method; the overhead is marginal, accounting for only 0.76% of a full-characterization time.

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Section: Cross-corner Variation Modelsmentioning

confidence: 99%

Cross-Corner Delay Variation Model for Standard Cell Libraries

Kim

Joo²,

Park

et al. 2021

IEEE Access

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“…Meanwhile, the aging sensors that were proposed by A. Amouri et al [27] place the aging sensor in a critical path to avoid late transitions occurring in the circuit. The aging sensor [28,29] and FPGA chips were reprogrammed to reduce the late transition effects caused by NBTI [30] and hot carrier injection (HCI). Meanwhile, M. Valdes-Pena proposed an aging sensor without determining a specific delay range [31].…”

Section: Lifetime Reliability Sensing In Fpgasmentioning

confidence: 99%

Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance

et al. 2021

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The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.

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“…Understanding this loop, for purposes of establishing design signoff criteria, has significant implications: (i) underestimation of aging increases lifetime energy consumption due to higher than expected supply voltage levels; and (ii) overestimation of aging increases layout area due to more pessimistic gate sizing to meet performance specifications at signoff. The work of [1] analyzes this chickenegg dependency and proposes a methodology for aging-aware signoff in an AVS-enabled system; the authors further quantify the power and area overheads due to improper selection of signoff corners. Figure 9 shows that substantial power or area overheads can result from improper choice of aging signoff corner.…”

Section: Avs-aware Margin Definitionmentioning

confidence: 99%

“…Tradeoff of average power (over 10-year lifetime) versus area, among circuit implementations signed off at different BTI aging corners, assuming DC BTI stress and AVS[1]. Left to right: (i) c2q delay vs. setup time; (ii) c2q delay vs. hold time; and (iii) setup time vs. hold time.…”

mentioning

confidence: 99%

New game, new goal posts

Kahng

2015

Proceedings of the 52nd Annual Design Automation Conference

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Timing closure is the most critical phase of modern systemon-chip implementation: without timing closure, there is no tapeout. Timing closure is the end result of (i) years of methodology development, script development, signoff recipe development, etc.; (ii) months of block-and toplevel final physical implementation; and (iii) a last set of manual noise and DRC fixes, with a final signoff analysis and physical verification. Over the past decade, key aspects of the underlying process and device technologies, modeling standards, EDA tooling, design methodology, and signoff criteria have changed the nature of timing closure. This paper surveys such recent evolutions in timing closure and notes directions for near-term future evolutions.

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On Aging-Aware Signoff for Circuits With Adaptive Voltage Scaling

Cited by 10 publications

References 22 publications

Cross-Corner Delay Variation Model for Standard Cell Libraries

Cross-Corner Delay Variation Model for Standard Cell Libraries

Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance

New game, new goal posts

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