On analysis and synthesis of (
            <i>n, k</i>
            )-non-linear feedback shift registers

Dubrova, Elena; Teslenko, Maxim; Tenhunen, Hannu

doi:10.1145/1403375.1403686

Cited by 23 publications

(14 citation statements)

References 18 publications

(16 reference statements)

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“…The architecture of the modular reduction stage is based on generators of Galois sequences; its properties are studied in [18]. From there it is observed that it was originally implemented by registers to obtain the n vectors corresponding to the partial residues.…”

Section: Finite Field Multipliersmentioning

confidence: 99%

“…If it is possible to define the LFSR model through a concurrent implementation [21], the area and power consumed are similar and even less compared to the sequential version [22]. For this, we analyzed optimizations on the circuit [18] and a mathematical model for the generation of the sub-sequences, considering that applications of high performance require parallel implementations [23].…”

Section: Finite Field Multipliersmentioning

confidence: 99%

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VHDL Optimized Model of a Multiplier in Finite Fields

Sandoval-Ruiz

2017

I&U:EfD

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How to cite this article: C. Sandoval-Ruiz, "VHDL optimized model of a multiplier in finite fields," Ing. Univ., vol. 21, no. 2, pp. 195-211, 2017 ResumenIntroducción: Este artículo presenta el modelo de un multiplicador en campos finito GF que estudia la arquitectura generalizada del componente LFSR (registros de desplazamiento con realimentación lineal), con el propósito de generar una descripción concurrente, aplicando conceptos de análisis estructural, descripción de componentes parametrizados y tratamiento matemático de señales. Método: El diseño se realizó tabulando los términos en función de las variables tiempo y posición en el circuito, del componente de reducción modular, con lo que se creó una matriz de operaciones combinacionales. Este modelo fue descrito en VHDL, para las pruebas de comportamiento y optimización del hardware. Resultados: La investigación permitió establecer las ecuaciones para la implementación del modelo en VHDL, en su expresión genérica con el operador "concatenación". Para la configuración de hardware se estimó el consumo de recursos en hardware, a nivel de operadores lógicos y se obtuvo una propuesta eficiente. Así mismo, se obtuvo un 7,89 % de ahorro del consumo de potencia asociada a la señal en el diseño del multiplicador, con la técnica de optimización propuesta. Conclusiones: El modelo desarrollado simplifica la descripción de circuitos paralelos, de alta eficiencia desde un enfoque de modelado matemático para descripción de hardware. El método propuesto muestra sus aportes en materia de optimización en el modelado eficiente de sistemas lógicos avanzados, el cual puede ser extrapolado a componentes más complejos.Palabras clave modelo VHDL; multiplicador en campos finitos; optimización circuital.

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Section: Finite Field Multipliersmentioning

confidence: 99%

Section: Finite Field Multipliersmentioning

confidence: 99%

VHDL Optimized Model of a Multiplier in Finite Fields

Sandoval-Ruiz

2017

I&U:EfD

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“…In [10] it is shown that NLFSRs are more resistant to cryptanalytic attacks than LFSRs. Using L cells NLFSRs, a cryptanalyst can take up to ( ) L 2 Ο [11] or as given in [12], a sequence of L (L 1) / 2 L ⋅ + + bits is necessary to determine the structure of L-bit NLFSR generating this sequence.…”

Section: Overview Of the Problem And Formulation Of Research Problemsmentioning

confidence: 99%

Development of the Search Method for Non-Linear Shift Registers Using Hardware, Implemented on Field Programmable Gate Arrays

Poluyanenko

2017

EUREKA: Physics and Engineering

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The nonlinear feedback shift registers of the second order inare considered, because based on them it can be developed a generator of stream ciphers with enhanced cryptographic strength. Feasibility of nonlinear feedback shift register search is analyzed. These registers form a maximal length sequence, using programmable logic devices. Performance evaluation of programmable logic devices in the generation of pseudo-random sequence by nonlinear feedback shift registers is given. Recommendations to increase this performance are given. The dependence of the maximum generation rate (clock frequency), programmable logic devices on the number of concurrent nonlinear registers is analyzed. A comparison of the generation rate of the sequences that are generated by nonlinear feedback shift registers is done using hardware and software. The author suggests, describes and explores the search method of nonlinear feedback shift registers, generating a sequence with a maximum period. As the main result are found non-linear 26, 27, 28 and 29 degrees polynomials.

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“…Although some sequences were listed in [1] that can be generated by (n,k)-NLFSRs instead of Fibonacci type of NLFSRs, there are many sequences that (n,k)-NLFSRs can not generate. So we have the Theorem 1 following:…”

Section: The Drawback Of (Nk)-nlfsrmentioning

confidence: 99%

“…Recently, an novel type of NLFSRs called (n,k)-NLFSRs [1] is presented. Each bit i in an (n,k)-NLFSR is updated according to its next-state function, which is a nonlinear function of the bit i+1 and up to k other bits.…”

Section: Introductionmentioning

confidence: 99%