2020
DOI: 10.1109/jetcas.2020.3040248
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On-Chip Error-Triggered Learning of Multi-Layer Memristive Spiking Neural Networks

Abstract: Recent breakthroughs in neuromorphic computing show that local forms of gradient descent learning are compatible with Spiking Neural Networks (SNNs) and synaptic plasticity. Although SNNs can be scalably implemented using neuromorphic VLSI, an architecture that can learn using gradientdescent in situ is still missing. In this paper, we propose a local, gradient-based, error-triggered learning algorithm with online ternary weight updates. The proposed algorithm enables online training of multilayer SNNs with me… Show more

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Cited by 30 publications
(25 citation statements)
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References 63 publications
(88 reference statements)
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“…For spiking neural networks, this property can prove important since gradient based methods have recently taken on renewed popularity in the training of such networks, especially through the use of surrogate gradient methods ( Neftci et al, 2019 ). An increasingly common practice, despite the lack of biological plausibility, is to use mini-batch GPU acceleration of spiking networks to train them more rapidly ( Neftci et al, 2017 ; Payvand et al, 2020 ). While researchers cite that future hardware will be able to more efficiently train using batch sizes of 1 ( Stewart et al, 2020 ), this has also frequently been proposed as the ideal batch size for using memristor-based artificial neural networks due to the memory overhead associated with gradient data.…”
Section: Resultsmentioning
confidence: 99%
“…For spiking neural networks, this property can prove important since gradient based methods have recently taken on renewed popularity in the training of such networks, especially through the use of surrogate gradient methods ( Neftci et al, 2019 ). An increasingly common practice, despite the lack of biological plausibility, is to use mini-batch GPU acceleration of spiking networks to train them more rapidly ( Neftci et al, 2017 ; Payvand et al, 2020 ). While researchers cite that future hardware will be able to more efficiently train using batch sizes of 1 ( Stewart et al, 2020 ), this has also frequently been proposed as the ideal batch size for using memristor-based artificial neural networks due to the memory overhead associated with gradient data.…”
Section: Resultsmentioning
confidence: 99%
“…The implementation of these two operations in memristive array will further improve the performance of the deep learning accelerators, while Hebbian-based learning algorithms could potentially bypass these operations. Online versions of Backprop, as discussed in section 3, are very recent and a memristive-based hardware demonstration is not yet available, despite some work in this direction is being done (Payvand et al, 2020b). To implement adaptation, biologically plausible algorithms able to cope with the non-ideal characteristics of memristive devices are needed.…”
Section: Applications Of Memristive Neural Networkmentioning
confidence: 99%
“…Online versions of Backprop, as discussed in section 3, are very recent and a memristive-based hardware demonstration is not yet available, despite some work in this direction is being done (Payvand et al, 2020b ). To implement adaptation, biologically plausible algorithms able to cope with the non-ideal characteristics of memristive devices are needed.…”
Section: Memristive Devices and Computingmentioning
confidence: 99%
“…Considering that in most practical applications, ANNs show very good performance, several works focus on the conversion of ANNs to SNNs [ 30 ]. Also, high performance deep SNNs were implemented with several learning methods [ 41 , 42 , 43 ] including gradient descent [ 44 , 45 ]. Other learning methods were developed for the detection of spatio-temporal patterns [ 46 , 47 ] and for evolving SNN [ 48 ].…”
Section: Related Workmentioning
confidence: 99%