On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture

Poehl, F.; Rzeha, J.; Beck, Matthias; Goessel, M.; Arnold, R.; Ossimitz, P.

doi:10.1109/ets.2006.34

Cited by 8 publications

(6 citation statements)

References 12 publications

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“…In multi-site testing, many dies on a load-board or even on a wafer are tested in parallel by the same ATE [1], [2], [3], [4], [5]. All the dies receive identical input by the ATE, but the output side of the die-under-test cannot be handled in the same straightforward way, as the defective dies will respond in many different, unpredictable ways.…”

Section: Introductionmentioning

confidence: 99%

“…One solution is feeding all the dies with the correct output by the ATE, equipping them with an on-chip comparator and comparing the expected and computed response on chip (figure 1). In a small on-chip memory the indices of the first n failing vectors or bits are stored and evaluated die by die [1], [6]. Throughput requirements and test application time are reduced, if each die is equipped with test data decompression and test response compaction logic (figure 2) [1].…”

Section: Introductionmentioning

confidence: 99%

“…In a small on-chip memory the indices of the first n failing vectors or bits are stored and evaluated die by die [1], [6]. Throughput requirements and test application time are reduced, if each die is equipped with test data decompression and test response compaction logic (figure 2) [1]. While time compactors and convolutional compactors are highly effective in general [7], [8], [9], they are not the optimal choice for implementing a stop-on-nth-fail strategy as the faulty signature is kept over multiple or even all clock cycles, and space compaction techniques are more appropriate [10], [11].…”

Section: Introductionmentioning

confidence: 99%

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A diagnosis algorithm for extreme space compaction

Holst¹

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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During volume testing, test application time, test data volume and high performance automatic test equipment (ATE) are the major cost factors. Embedded testing including builtin self-test (BIST) and multi-site testing are quite effective cost reduction techniques which may make diagnosis more complex. This paper presents a test response compaction scheme and a corresponding diagnosis algorithm which are especially suited for BIST and multi-site testing. The experimental results on industrial designs show, that test time and response data volume reduces significantly and the diagnostic resolution even improves with this scheme. A comparison with X-Compact indicates, that simple parity information provides higher diagnostic resolution per response data bit than more complex signatures.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A diagnosis algorithm for extreme space compaction

Holst¹

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…Bandwidth reduction is one of the major concerns for multisite testing [1,2]. Reducing bandwidth on the output side affects input side bandwidth, if fault coverage and diagnostic resolution should be maintained.…”

Section: Introductionmentioning

confidence: 99%

Test Encoding for Extreme Response Compaction

Kochte

Holst

Elm

et al. 2009

2009 14th IEEE European Test Symposium

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Optimizing bandwidth by compression and compaction always has to solve the trade-off between input bandwidth reduction and output bandwidth reduction. Recently it has been shown that splitting scan chains into shorter segments and compacting the shift data outputs into a single parity bit reduces the test response data to one bit per cycle without affecting fault coverage and diagnostic resolution if the compactor's structure is included into the ATPG process.This test data reduction at the output side comes with challenges at the input side. The bandwidth requirement grows due to the increased number of chains and due to a drastically decreased amount of don't care values in the test patterns.The paper at hand presents a new iterative approach to test set encoding which optimizes bandwidth on both input and output side while keeping the diagnostic resolution and fault coverage. Experiments with industrial designs demonstrate that test application time, test data volume and diagnostic resolution are improved at the same time and for most designs testing with a bandwidth of three bits per cycle is possible.

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“…The latter is important since unspecified bits in the PR are becoming more common with technology scaling. A similar approach with a mechanism for masking unspecified values has been proposed for different purpose [12]. The scan chains, a to d in c 1 and e to g in c 2 , are partitioned into wrapper chains that are connected to six TAM wires, TAM 1 to TAM 6 .…”

Section: Sharingmentioning

confidence: 99%