On-chip face recognition system design with memristive Hierarchical Temporal Memory

Abstract

Hierarchical Temporal Memory is a new machine learning algorithm intended to mimic the working principle of neocortex, part of the human brain, which is responsible for learning, classification, and making predictions. Although many works illustrate its effectiveness as a software algorithm, hardware design for HTM remains an open research problem. Hence, this work proposes an architecture for HTM Spatial Pooler and Temporal Memory with learning mechanism, which creates a single image for each class based on important and unimportant features of all images in the training set. In turn, the reduction in the number of templates within database reduces the memory requirements and increases the processing speed. Moreover, face recognition analysis indicates that for a large number of training images, the proposed design provides higher accuracy results (83.5%) compared to only Spatial Pooler design presented in the previous works.

Hierarchical Temporal Memory Using Memristor Networks: A Survey

“…Recent research illustrated the modified implementation of the analog HTM SP and analog hardware design of the HTM TM [12]. Comparing to the previous works [10], [11], [25], the modified HTM SP analog circuit level implementation is more scalable and introduces randomization process, which is more accurate and closer to the original HTM SP algorithm. The overall modified HTM SP architecture is illustrated in Fig.…”

“…3) Memristive HTM System: The analog implementation of the overall HTM system for face recognition is proposed in [25]. The system involves the input data controller, HTM SP, HTM TM, output data controller and pattern matcher.…”

“…In all HTM implementations [12], [30], [13], [11], [10], [25], the HTM weights are programmed as particular resistive states of the memristor. As the memristor is a device that can exhibit various resistive states between R ON and R OF F and possesses a non-volatility property, it can be programmed applying a pulse of a certain duration and amplitude across the Figure 12.…”

Neuromemristive Circuits for Edge Computing: A Review

“…The system is tested for face with AR database and speech recognition with TIMIT database, achieving the accuracy of 87% and 95%, respectively. There are several other HTM related works that propose different variations of hardware for memristive HTM [129], [130]. [86], [131], speech recognition (95%) [8], handwritten digits recognition (95%) [87] Partially scalable Implementation of full system performance, implementation of the exact algorithm for HTM SP and HTM TM, implementation of sequence learning in HTM TM Improvement of CMOS components to ensure scalability…”

Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits

“…The other learning architecture, where the proposed circuit can be used is HTM. There are several hardware implementations proposed for the HTM SP and HTM TM [62], [39], [40]. However, the learning stage of the HTM SP has not been implemented on hardware yet.…”