On-Chip Inductor Technique for Improving LNA Performance Operating at 15 GHz

Abstract

This paper presents a technique for low noise figure reduction of low-noise amplifier (LNA). The proposed LNA is designed in a source degeneration technique that offers lower noise figure. The resistance of the on-chip inductor is reduced by using multilayer that significantly reduces the thermal noise due to spiral inductor. Also, using spiral inductor as a gate inductor reduces the effect of the input parasitic capacitance on the noise figure and provides a good matching at the input and output of the LNA. The results of the LNA using multilayer on-chip inductor compared will off-chip inductor have been illustrated. It shows that the proposed technique reduces significantly the noise figure and improves the matching. The proposed LNA is designed in 0.13 μm process with 1.3 V supply voltage and simulated using Advanced Design System (ADS) software. The simulation results show that the LNA is unconditionally stable and provides a forward gain of 11.087 dB at operating frequency of 15 GHz with 1.784 dB noise figure and input and output impedance matching of -17.93 dB, and -10.04 dB.

Design of a high performance narrowband low noise amplifier using an on-chip orthogonal series stacked differential fractal inductor for 5G applications

“…Consequently, the effective on-chip area to implement an LNA using the proposed OSSDFI is much less. The multilayer implementation reduces the series resistance of the inductor [30]. The proposed OSSDFI has very low series resistance as shown in Table 2.…”

“…The gate inductor ( L g ) provides input matching and the large value of gate inductance reduces the NF [30].…”

“…The cascode LNA circuit topology with inductive source degeneration has better input matching, high gain, good stability, and low NF [22][23][24][25][26][27][28]. The on-chip inductor implementation of LNA reduces the spectral noise and provides good input and output matching [29,30].…”

Low Noise Amplifier at 60 GHz Using Low Loss On-Chip Inductors

“…Due to conductive nature of the substrate, on-chip spiral inductor experiences substantial loss, thereby reducing its quality (Q) factor. Also, to subside the problem of attaining self-resonance of spiral inductors at higher frequencies, various alternate design approaches have been followed [5][6][7][8][9][10][11]. Tis work presents the technique of employing low loss, on-chip inductors in the design of LNA with an aim of improving its gain and noise performance.…”

“…In papers [5,6], authors have proposed parallel stacked spiral inductor design formed by multimetal layers that intended to reduce series resistance and mitigate substrate efects. In [7], varying metal strips that balances ohmic loss and eddy current loss has been reported to achieve optimal Q-factor.…”