On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

Fujii, M.; Suzuki, Hiroaki; Notani, H.; Makino, Hiroshi; Shinohara, Hirofumi

doi:10.1109/esscirc.2008.4681841

“…[9] proposes an on-chip leakage current sensor for measuring D2D process variation. A leakage current sensor is used for compensating process variation [10], [11]. Band-gap reference based temperature sensors are proposed for high accuracy [12].…”

Section: Prior Workmentioning

confidence: 99%

“…By measuring multiple instances of the leakage current driven inverter delay, we can perform statistical operation. As variation is dominant in scaled CMOS process, the variance of the logarithm of fall delay, , in (5) can be approximated as follows: (11) The second term in the right hand side of the equation corresponds to the logic threshold variation of the following inverter. We will show in Section VI that logic threshold variation can be made negligible.…”

Section: F Process Variation Effectmentioning

confidence: 99%

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Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring

Islam

¹

,

Shiomi

²

,

Ishihara

³

et al. 2015

IEEE J. Solid-State Circuits

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Variation in process, voltage and temperature is a major obstacle in achieving energy-efficient operation of LSI. This paper proposes an all-digital on-chip circuit to monitor leakage current variations of both of the nMOSFET and pMOSFET independently. As leakage current is highly sensitive to threshold voltage and temperature, the circuit is suitable for tracking process and temperature variation. The circuit uses reconfigurable inhomogeneity to obtain statistical properties from a single monitor instance. A compact reconfigurable inverter topology is proposed to implement the monitor circuit. The compact and digital nature of the inverter enables cell-based design, which will reduce design costs. Measurement results from a 65 nm test chip show the validity of the proposed circuit. For a 124 sample size for both of the nMOSFET and pMOSFET, the monitor area is 4500 µm 2 and active power consumption is 76 nW at 0.8 V operation. The proposed technique enables area-efficient and low-cost implementation thus can be used in product chips for applications such as dynamic energy and thermal management, testing and post-silicon tuning.Index Terms-Leakage current, MOSFET, on-chip sensor, process variation, reconfigurable, ring oscillator, temperature. I. INTRODUCTIONV ARIATION in PVT (Process, Voltage and Temperature) has become a major performance limiting factor in scaled CMOS process [1]. For high performance applications such as processors, peak performance is often limited by the power/thermal budget [2]. Many chips operate in environmental conditions with high temperature. High temperature accelerates transistor aging causing severe reliability problems. High temperature increases leakage current causing serious energy loss. Especially for low-power and energy-aware applications, leakage power becomes a limiting factor in terms of battery life. Energy-efficient operation of LSI can be related to effective management of leakage energy. Thus, dynamic management of energy and temperature of chips has become a necessity.

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“…[9] proposes an on-chip leakage current sensor for measuring D2D process variation. A leakage current sensor is used for compensating process variation [10,11]. Band-gap reference based temperature sensors are proposed for high accuracy [12].…”

Section: Prior Workmentioning

confidence: 99%

“…Table III shows the values of the two terms in the right hand side of Eq. (11). The table compares the contribution of logic threshold variation for monitor cell structures of different stack numbers.…”

Section: ) Delay Characteristicsmentioning

confidence: 99%

Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring

Islam

¹

,

Shiomi

²

,

Ishihara

³

et al. 2014

2014 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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Variation in process, voltage and temperature is a major obstacle in achieving energy-efficient operation of LSI. This paper proposes an all-digital on-chip circuit to monitor leakage current variations of both of the nMOSFET and pMOS-FET independently. As leakage current is highly sensitive to threshold voltage and temperature, the circuit is suitable for tracking process and temperature variation. The circuit uses reconfigurable inhomogeneity to obtain statistical properties from a single monitor instance. A compact reconfigurable inverter topology is proposed to implement the monitor circuit. The compact and digital nature of the inverter enables cell-based design, which will reduce design costs. Measurement results from a 65-nm test chip show the validity of the proposed circuit. For a 124 sample sizes for both of the nMOSFET and pMOSFET, the monitor area is 4500 µm 2 and active power consumption is 76 nW at 0.8 V operation. The proposed technique enables area-efficient and low-cost implementation thus can be used in product chips for applications such as dynamic energy and thermal management, testing and post-silicon tuning.

show abstract

A novel adaptive reverse body bias technique to minimize standby leakage power and compensate process and temperature variations

Xiao

¹

,

Liu

²

,

Sun

³

2011

Proceedings of 2011 Cross Strait Quad-Regional Radio Science and Wireless Technology Conference

2

0

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On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

Cited by 5 publications

References 12 publications

Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring

Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring

Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring

A novel adaptive reverse body bias technique to minimize standby leakage power and compensate process and temperature variations

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