On-chip matched 5.2 and 5.8 GHz differential LNAsfabricated using 0.35 µm CMOS technology

Runge, K.; Pehlke, D.R.; Schiffer, B.

doi:10.1049/el:19991250

Cited by 19 publications

(5 citation statements)

References 2 publications

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“…Based on these results, we integrated the series-type SW with a gate width of 200 m on the single-chip IC. As can be seen in this figure, both the simulated and measured characteristics for the series-type SW are in good agreement with each other, proving that the simple equations (1)- (11) are useful for predicting the transfer characteristics of the series-type SW. Fig. 6(a) and (b) shows the measured frequency response and power handling capability, respectively, for the series-type SW incorporated into the IC in transmit mode.…”

Section: A T/r-switchsupporting

confidence: 69%

A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMIC front-end with a low insertion loss switch

Yamamoto

Heima

Furukawa

et al. 2001

IEEE J. Solid-State Circuits

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This paper describes the design and experimental results of a 1.8-V single-chip CMOS MMIC front-end for 2.4-GHz band short-range wireless communications, such as Bluetooth and wireless LANs. The IC consists of fundamental RF building circuits-a power amplifier (PA), a low-noise amplifier (LNA), and a transmit/receive-antenna switch (SW), including almost all on-chip matching elements. The IC was fabricated using a 0.18-m standard bulk CMOS technology which has no extra processing steps to enhance the RF performances. Two new circuit-design techniques are introduced in the IC in order to minimize the insertion loss of the SW and realize a higher gain for the PA and LNA despite the utilization of the standard bulk CMOS technology. The first is the derivation of an optimum gate width of the SW to minimize the insertion loss based on small-signal equivalent circuit analysis. The other is the revelation of the advantages of interdigitated capacitors (IDCs) over conventional polysilicon to polysilicon capacitors and the successful use of the IDCs in the LNA and PA. The IC achieves the following sufficient characteristics for practical wireless terminals at 2.4 GHz and 1.8 V: a 5-dBm transmit power at a 1-dB gain compression, a 19-dB gain, an 18-mA current for the PA, a 1.5-dB insertion loss, more than 24-dB isolation, an 11-dBm power handling capability for the SW, a 7.5-dB gain, a 4.5-dB noise figure, and an 8-mA current for the LNA.

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Section: A T/r-switchsupporting

confidence: 69%

A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMIC front-end with a low insertion loss switch

Yamamoto

Heima

Furukawa

et al. 2001

IEEE J. Solid-State Circuits

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show abstract

“…For example, single-chip wireless transceivers have been fabricated in 0.25-at 1.8 GHz for DCS-1800 wireless communications and at 2.45 GHz for Bluetooth applications [9], [10]. Advances in deep submicron CMOS will also make single-chip CMOS wireless transceivers at 5-6 GHz band feasible [11], [12]. Single-chip solutions have employed the zero-or low-IF architectures for the wireless transceivers.…”

Section: Introductionmentioning

confidence: 99%

Finite-Difference Time-Domain Analysis of Integrated Ceramic Ball Grid Array Package Antenna for Highly Integrated Wireless Transceivers

Zhang

2004

IEEE Trans. Antennas Propagat.

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“…The figure indicates that, owing to technology scaling, the cutoff frequency of NMOS devices has increased to approximately 100GHz. It not only promises gigahertz integration and gigahertz clock rate, but also arouses great expectations for CMOS RF circuits at 1GHz−6GHz or even higher frequencies [23][24][25][26], where the dominant technology is currently silicon bipolar and GaAs. Figure 2.1 Progress of the cutoff frequency in several processes [22] In the last few years, various CMOS RF chips have been implemented.…”

Section: Technology Trends In Rficsmentioning

confidence: 99%

Dual band low-noise amplifier designs for bluetooth and hiperLAN applications

Mou¹

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The last decade saw an explosion of wireless communication technology, together with a rapid development of consumer demand for information. Intensive research efforts have focused on a lot of application areas, such as mobile cellular phones, coreless telephones, global positioning system (GPS), wireless short-distance communication and wireless local area network communication (WLAN/HiperLAN). With so many coexistent communication standards, it is necessary to develop a single-chip transceiver, which can adapt to several bands at the same time. One of the crucial bottlenecks for the multi-standard communications is how to design a low noise amplifier (LNA) that can operate in different frequency bands, as the LNA serves as the first amplification block in the receiving chains. It is also known that, with the scalability of CMOS technology, the obtained cutoff frequency (f T) could be up to one hundred gigahertz. However, the passive on-chip inductors implemented with the current CMOS process are usually lossy and bulky. This is a very significant problem in LNA design, especially in the input stage design using source inductive degeneration architecture. To make the circuit compact and fully integrated, research efforts should be done to reduce the required inductor number and inductor value. Based on the above-mentioned concerns, the investigation on the designs of dual-band LNAs, as well as a modified architecture used for input matching in CMOS LNAs to make the circuit more compact, is presented in this thesis. According to the proposed investigation, a narrow-band LNA (LNA1), a wideband LNA (LNA3) and

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On-chip matched 5.2 and 5.8 GHz differential LNAsfabricated using 0.35 µm CMOS technology

Cited by 19 publications

References 2 publications

A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMIC front-end with a low insertion loss switch

A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMIC front-end with a low insertion loss switch

Finite-Difference Time-Domain Analysis of Integrated Ceramic Ball Grid Array Package Antenna for Highly Integrated Wireless Transceivers

Dual band low-noise amplifier designs for bluetooth and hiperLAN applications

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