On-Chip Optical Interconnect for Low-Power

O’Connor, Ian; Gaffiot, F.

doi:10.1007/1-4020-8076-x_2

Cited by 34 publications

(18 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Such an architecture can be implemented in a single layer. As an intermediate approach, a combination of electronic and optical interconnects on a chip has been proposed, using the relatively long and highbandwidth optical links to distribute data and/or clock signals over the chip surface to smaller areas of the chip, while maintaining the electronic interconnects within these smaller areas [10]. We further note that connections to sources and detectors can be small, in the order of 30-50 μm pitch and at 15-25 μm width.…”

mentioning

confidence: 99%

Hybrid Silicon Photonics for Optical Interconnects

Heck

Chen

Fang

et al. 2011

IEEE J. Select. Topics Quantum Electron.

202

View full text Add to dashboard Cite

Abstract-In this paper, we review the hybrid silicon photonic integration platform and its use for optical links. In this platform, a III/V layer is bonded to a fully processed silicon-on-insulator wafer. By changing the bandgap of the III/V quantum wells (QW), lowthreshold-current lasers, high-speed modulators, and photodetectors can be fabricated operating at wavelengths of 1.55 μm. With a QW intermixing technology, these components can be integrated with each other and a complete high-speed optical interconnect can be realized on-chip. The hybrid silicon bonding and process technology are fully compatible with CMOS-processed wafers because high-temperature steps and contamination are avoided. Full wafer bonding is possible, allowing for low-cost and large-volume device fabrication.

show abstract

mentioning

confidence: 99%

Hybrid Silicon Photonics for Optical Interconnects

Heck

Chen

Fang

et al. 2011

IEEE J. Select. Topics Quantum Electron.

202

View full text Add to dashboard Cite

show abstract

“…1͑c͒ for n = 4, as proposed by O'Connor and Gaffiot. 9 The network has a simple layout consisting of four bus waveguides, two straight and two 90-deg bents, composed appropriately to form six intersections in four rows ͑each row corresponding to a specific wavelength͒. These intersections form the center of six wavelength-selective filters.…”

Section: Optical Network Principlesmentioning

confidence: 99%

Synthesis of highly integrated optical network based on microdisk-resonator add-drop filters in silicon-on-insulator technology

Kaźmierczak¹,

Dortu²,

Giannone³

et al. 2009

Opt. Eng

View full text Add to dashboard Cite

Abstract. We analyze a highly compact optical add-drop filter topology based on a pair of microdisk resonators and a bus waveguide intersection. The filter is further assessed on an integrated optical 4 ϫ 4 network for optical on-chip communication. The proposed network structure, as compact as 50ϫ 50 m, is fabricated in a CMOS-compatible process on a silicon-on-insulator ͑SOI͒ substrate. Finally, the experimental results demonstrate the proper operation of the fabricated devices.

show abstract

“…Much current research focuses on making processors more power efficient and one approach is to add optical connections or lasers onto processors [4,9,11,13,15,21,22,36]. This technology is promised to bring about many advancements.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, power usage is less as transmitting an optical signal scales to long distances while taking nearly the same energy for shorter distances [21,27]. We model on-chip photonics capabilities by adding "optical" connections or optics to the mesh.…”

Section: Introductionmentioning

confidence: 99%

An Optimal Time-Power Tradeoff for Sorting on a Mesh-Connected Computer with On-Chip Optics

Poon

Stout

2014

IJNC

View full text Add to dashboard Cite

Energy consumption has become a critical factor constraining the design of massively parallel computers, necessitating the development of new models and energy-efficient algorithms. The primary component of on-chip energy consumption is data movement, and the mesh computer is a natural model of this, explicitly taking distance into account. Unfortunately the dark silicon problem increasingly constrains the number of bits which can be moved simultaneously. For sorting, standard mesh algorithms minimize time and total data movement, and hence constraining the mesh to use only half its processors at any instant must double the time. It is anticipated that on-chip optics will be used to minimize the energy needed to move bits, but they have constraints on their layout. In an abstract model, we show that a pyramidal layout and a new power-aware algorithm allows one to sort with only a square root increase in time as the fraction of processors simultaneously powered decreases. Furthermore, this layout is shown to be optimal in terms of the time-power tradeoff required for sorting. Previous algorithms assumed fully powered systems, hence pyramid sorting was of no interest since when fully powered they are no faster than the base mesh. Our results show asymptotic theoretical limits of computation and energy usage on a model which takes physical constraints and developing interconnection technology into account.

show abstract

On-Chip Optical Interconnect for Low-Power

Cited by 34 publications

References 16 publications

Hybrid Silicon Photonics for Optical Interconnects

Hybrid Silicon Photonics for Optical Interconnects

Synthesis of highly integrated optical network based on microdisk-resonator add-drop filters in silicon-on-insulator technology

An Optimal Time-Power Tradeoff for Sorting on a Mesh-Connected Computer with On-Chip Optics

Contact Info

Product

Resources

About