On-chip repair and an ATE independent fusing methodology

Cowan, B.; Farnsworth, O.; Jakobsen, P.; Oakland, S.F.; Ouellette, M.R.; Wheater, D.L.

doi:10.1109/test.2002.1041759

Cited by 11 publications

(2 citation statements)

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“…Then the MBIST controller checks memories by running specified algorithms. If any new faults are detected, they are corrected using the soft repair technique presented in [59]. The time taken for loading data from OTP is critical as it adds to boot time.…”

Section: In-field Repairmentioning

confidence: 99%

Memory built-in self-repair and correction for improving yield: a review

Sontakke,

Atchina

2024

IJECE

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Nanometer memories are highly prone to defects due to dense structure, necessitating memory built-in self-repair as a must-have feature to improve yield. Today’s system-on-chips contain memories occupying an area as high as 90% of the chip area. Shrinking technology uses stricter design rules for memories, making them more prone to manufacturing defects. Further, using 3D-stacked memories makes the system vulnerable to newer defects such as those coming from through-silicon-vias (TSV) and micro bumps. The increased memory size is also resulting in an increase in soft errors during system operation. Multiple memory repair techniques based on redundancy and correction codes have been presented to recover from such defects and prevent system failures. This paper reviews recently published memory repair methodologies, including various built-in self-repair (BISR) architectures, repair analysis algorithms, in-system repair, and soft repair handling using error correcting codes (ECC). It provides a classification of these techniques based on method and usage. Finally, it reviews evaluation methods used to determine the effectiveness of the repair algorithms. The paper aims to present a survey of these methodologies and prepare a platform for developing repair methods for upcoming-generation memories.

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Section: In-field Repairmentioning

confidence: 99%

Memory built-in self-repair and correction for improving yield: a review

Sontakke,

Atchina

2024

IJECE

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“…this reduces to (4). When α → ∞, the values of λ 0 for different chips are totally uncorrelated, and therefore, the probability distribution function of λ [i.e., f (λ)] can be considered as a Dirac pulse on λ 0 .…”

Section: Global Yield Modelmentioning

confidence: 99%

Evaluating the Yield of Repairable SRAMs for ATE

Ottavi

Schiano

Wang

et al. 2006

IEEE Trans. Instrum. Meas.

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Abstract-An accurate yield evaluation is essential in selecting redundancy allocation and testing strategies for memories. Yield evaluation can resolve the many issues revolving around costeffective built-in self-test (BIST) and automatic test equipment (ATE)-based solutions for a higher test transparency. In this paper, two yield-calculation methodologies for SRAM arrays are proposed. General yield expressions for VLSI chips are initially presented. The regular and repetitive structure of an SRAM array is exploited, and substantial yield improvements can be achieved by the introduction of redundancy. Two repair yield-evaluation methods for one-dimensional redundant memory arrays are introduced and compared for ATE application. The first method is based on the sum of the probabilities of all repairable fault patterns; the second method is based on Markov modeling. Using industrial data, it is shown that these methods are applicable to ATE usage under different conditions of defect rate in the possible defects. Different features of the proposed methods are discussed.

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An embedded non-volatile FRAM with electrical fuse repair scheme and one time programming scheme for high performance smart cards

Min

Lee

et al.

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.

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On-chip repair and an ATE independent fusing methodology

Cited by 11 publications

References 1 publication

Memory built-in self-repair and correction for improving yield: a review

Memory built-in self-repair and correction for improving yield: a review

Evaluating the Yield of Repairable SRAMs for ATE

An embedded non-volatile FRAM with electrical fuse repair scheme and one time programming scheme for high performance smart cards

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