On Cloud-Supported Web-Based Integrated Development Environment for Programming DataFlow Architectures

Korolija, Nenad; Zamuda, Aleš

doi:10.1007/978-3-030-13803-5_2

Cited by 3 publications

(1 citation statement)

References 24 publications

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“…Much work has been performed to support programming dataflow hardware. Some of them focus on the availability of dataflow hardware in the cloud as well as providing an integrated development environment for programming [13]. Others tried to provide automatic parallelization of control-flow algorithms onto the dataflow hardware [14,15].…”

Section: Methodsmentioning

confidence: 99%

Merging control-flow and dataflow architectures on a single chip

Korolija,

Štrbac-Savić

2024

J Comp Foren Sci

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Computing power rises predominantly by increasing the number of cores in modern processors and the number of processors in cluster and cloud architectures. Along with increasing processing power, high-performance computing requirements also rise. The majority of the computing infrastructure includes control-flow processors that are based on the von Neumann paradigm. On the contrary, the principle of dataflow architectures is based on the data flowing through the already configured hardware. Recent research has proposed hybrid architectures, where both control-flow and dataflow hardware would exist on the same chip die. This article proposes a new hybrid control-flow and dataflow architecture where the control-flow hardware resembles modern graphical cards with thousands of cores and each GPU core has a reasonable amount of data-flow hardware. In this way, the advantages of dataflow architecture are exploited, including faster processing of high-performance computing algorithms and lower power consumption, while the conventional problem of communicating between control-flow and dataflow architectures is minimized. The proposed architecture is tested by analyzing the conjugate gradient method executed on both control-flow and dataflow hardware. The execution of the algorithm is divided onto GPU cores, and the execution of repeated instructions on each GPU core is delegated to the assigned dataflow hardware. The results indicate that it is possible to accelerate the execution of algorithms using the proposed architecture.

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Section: Methodsmentioning

confidence: 99%

Merging control-flow and dataflow architectures on a single chip

Korolija,

Štrbac-Savić

2024

J Comp Foren Sci

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Drawbacks of Programming Dataflow Architectures and Methods to Overcome Them

Korolija

2024

Lecture Notes in Networks and Systems

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Towards hybrid supercomputing architectures

Korolija¹,

Milfeld²

2022

J Comp Foren Sci

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In light of recent work on combining control-flow and dataflow architectures on the same chip die, a new architecture based on an asymmetric multicore processor is proposed. The control-flow architectures are described as a most commonly used computer architecture today. Both multicore and manycore architectures are explained, as they are based on the same principles. A dataflow computing model assumes that data input flows through hardware as either a software or hardware dataflow implementation. In software dataflow, processors based on the control-flow paradigm process tasks based on their availability from the same queue (if there are any). In hardware dataflow architectures, the hardware is configured for a particular algorithm, and data input is streamed into the hardware, and the output is streamed back to the multicore processor for further processing. Hardware dataflow architectures are usually implemented with FPGAs. Hybrid architectures employ asymmetric multicore and manycore computer architectures that are based on the control-flow and hardware dataflow architecture, all combined on the same chip die. Advantages include faster processing time, lower power consumption (and heating), and less space needed for the hardware.

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On Cloud-Supported Web-Based Integrated Development Environment for Programming DataFlow Architectures

Cited by 3 publications

References 24 publications

Merging control-flow and dataflow architectures on a single chip

Merging control-flow and dataflow architectures on a single chip

Drawbacks of Programming Dataflow Architectures and Methods to Overcome Them

Towards hybrid supercomputing architectures

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