On-CMOS Image Sensor Processing for Lane Detection

Lee, So‐Yeon; Jeong, Bohyeok; Park, Keunyeol; Song, Minkyu; Kim, Soo Youn

doi:10.3390/s21113713

Cited by 11 publications

(2 citation statements)

References 14 publications

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“…For proper operation in time or hybrid mode, ADC linearity must be assured (e.g., using a variable ADC clock frequency). There are also similar image processing solutions in column-parallel SS AD converters [20][21][22]. Max.…”

Section: Discussionmentioning

confidence: 99%

In-ADC, Rank-Order Filter for Digital Pixel Sensors

Kłosowski,

Sun,

Jendernalik

et al. 2023

Electronics

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This paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS photogates, was fabricated using a standard 180 nm CMOS process. The measurement results demonstrate the full functionality of the novel filter concept, with image acquisition in both single-sampling and correlated-double-sampling (CDS) modes (CDS is digitally performed using ADCs). The experimental, massively parallel rank-order filter can process 650 frames per second with a power consumption of 4.81 mW.

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Section: Discussionmentioning

confidence: 99%

In-ADC, Rank-Order Filter for Digital Pixel Sensors

Kłosowski,

Sun,

Jendernalik

et al. 2023

Electronics

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“…Examples of such devices are Smart Image Sensors (SIS) [ 29 ], which integrate image capture and processing on the same die. The image processing hardware can be integrated at the pixel, column, or chip level [ 3 ], increasing the parallelism available to the algorithm and throughput of the implementation while reducing latency, memory requirements, and power consumption [ 30 , 31 ].…”

Section: Introductionmentioning

confidence: 99%

A CMOS Image Readout Circuit with On-Chip Defective Pixel Detection and Correction

López-Portilla

Valenzuela

Zarkesh-Ha

et al. 2023

Sensors

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Images produced by CMOS sensors may contain defective pixels due to noise, manufacturing errors, or device malfunction, which must be detected and corrected at early processing stages in order to produce images that are useful to human users and image-processing or machine-vision algorithms. This paper proposes a defective pixel detection and correction algorithm and its implementation using CMOS analog circuits, which are integrated with the image sensor at the pixel and column levels. During photocurrent integration, the circuit detects defective values in parallel at each pixel using simple arithmetic operations within a neighborhood. At the image-column level, the circuit replaces the defective pixels with the median value of their neighborhood. To validate our approach, we designed a 128×128-pixel imager in a 0.35μm CMOS process, which integrates our defective-pixel detection/correction circuits and processes images at 694 frames per second, according to post-layout simulations. Operating at that frame rate, our proposed algorithm and its CMOS implementation produce better results than current state-of-the-art algorithms: it achieves a Peak Signal to Noise Ratio (PSNR) and Image Enhancement Factor (IEF) of 45 dB and 198.4, respectively, in images with 0.5% random defective pixels, and a PSNR of 44.4 dB and IEF of 194.2, respectively, in images with 1.0% random defective pixels.

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Concurrent Image Differentiation and Integration Processings Enabled By Polarization‐Multiplexed Metasurface

Bi,

Wu,

Fan

et al. 2024

Laser & Photonics Reviews

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Optical computing and image processing performed by sensor front‐end metasurfaces is receiving increasing interest because of advantages such as significant reduction of latency time, energy consumption, and system complexity. Despite the rapid progress, concurrent processing, the most important feature of electronic computing, has not yet been well implemented in optical computing. Here, a metasurface‐based optical image processor that can perform optical differentiation and integration tasks simultaneously is proposed. This optical front‐end processor integrates two coherent transfer functions corresponding to differential and integral convolution kernels into a built‐in metasurface by polarization encoding, allowing concurrent processing of multiple all‐optical computational tasks. The simultaneous differentiation and integration operations on images for edge enhancement and denoising are demonstrated at multiple visible wavelengths. This concurrent processing architecture paves a promising pathway toward multifunctional and higher‐speed image processing for machine vision and biomedical imaging and shows the potential to expedite and potentially supplant certain digital neural network algorithms.

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On-CMOS Image Sensor Processing for Lane Detection

Cited by 11 publications

References 14 publications

In-ADC, Rank-Order Filter for Digital Pixel Sensors

In-ADC, Rank-Order Filter for Digital Pixel Sensors

A CMOS Image Readout Circuit with On-Chip Defective Pixel Detection and Correction

Concurrent Image Differentiation and Integration Processings Enabled By Polarization‐Multiplexed Metasurface

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