ON current enhancement and variability suppression in tunnel FETs by the isoelectronic trap impurity of beryllium

Abstract

We have experimentally demonstrated ON current enhancement and variability suppression of Si tunnel FETs (TFETs) by introducing an isoelectronic trap (IET) beryllium into the channel. In the previous studies, it was showed that the introduction of the Al-N IET impurity enables those requirements for Si-TFETs. In this study, we focused on Be as a new IET impurity and introduced the new IET into Si-TFETs. We found the optimum conditions for the formation of the Be-IET state in Si and demonstrated process integration of the Be-IET formation and TFET fabrication. The Be-introduced TFET exhibits five times enhancement of ON current; this enhancement ratio is larger than the case of the Al-N IET. Furthermore, significant suppression of the variability is achieved by Be-IET as well as the previous case of the Al-N IET. This better ON current improvement by Be-IET results from the energy level of Be deeper than that of Al-N IET, which plays a better role in enhancing the performance of Si-TFETs.

Introduction of deep level impurities, S, Se, and Zn, into Si wafers for high-temperature operation of a Si qubit

“…Differences in S, Zn, and Se introduction and PIA conditions may affect the results. Defect-related emission lines 6,34) such as the X-line (1.018 eV) 35) and W-line (1.040 eV), 36) which have been observed in ion-irradiated Si, were also not observed. These results from Figs.…”

“…Thus, we focused on group II−VI elements that form deep impurity levels in Si. In our previous study, 6) we introduced Be into Si wafers and confirmed the formation of impurity levels by photoluminescence, and conducted experiments to introduce Be into Si devices.…”

Resonant tunneling and quantum interference of a two-spin system in silicon tunnel FETs

“…12,13) Recently, we also reported that beryllium and the group II element, Zn, and group VI elements, S and Se, were introduced into a Si wafer to form deep levels in a TFET. 14,15) Figure 1(c) shows a charge-stability diagram, and Fig. 1(d) shows the typical current-drain bias (I s -V d ) characteristics of an Al-N-implanted TFET with a channel length of 70 nm.…”