On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster

Rogenmoser, Michael; Wistoff, Nils; Vogel, Pirmin; Gürkaynak, Frank K.; Benini, Luca

doi:10.1109/isvlsi54635.2022.00089

Cited by 9 publications

(4 citation statements)

References 10 publications

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“…While the tight coupling and integration with the memory system significantly improve the processing performance of parallelizable tasks, these cores can also be used for the same calculation, offering a redundancy copy to detect errors. Extending the hardware, on-demand redundancy grouping (ODRG) [46] combines three cores in the PULP cluster into a triple-core lockstep (TCLS) group. In an 8-core cluster, this allows for two TCLS groups, and 2 remaining individual cores.…”

Section: On-demand Redundancy Grouping (Odrg)mentioning

confidence: 99%

PULP Fiction No More—Dependable PULP Systems for Space

Ulbricht

Tortorella

Rogenmoser³

et al. 2023

2023 IEEE European Test Symposium (ETS)

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Due to their flexibility and openness, the RISC-V ISA and processor architectures have emerged as notable contenders in various application domains. Their advantages over commercial solutions have attracted the interest of academia and industry and even led to their planned adoption in aeronautics and space. However, in these demanding environments, system reliability is of paramount importance. To address this issue, this paper presents an overview of several hardware-centric approaches for developing reliable systems based on the parallelultra low power (PULP) open-source RISC-V hardware platform. These approaches range from gate-level optimizations to systemlevel improvements and highlight the versatility of the PULP architecture and its potential as a viable architecture for developing various aerospace platforms.

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Section: On-demand Redundancy Grouping (Odrg)mentioning

confidence: 99%

PULP Fiction No More—Dependable PULP Systems for Space

Ulbricht

Tortorella

Rogenmoser³

et al. 2023

2023 IEEE European Test Symposium (ETS)

Self Cite

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“…With a 2-stage pipeline and independent instruction and data memory interfaces, the lightweight core is designed for high area efficiency, while providing reasonable performance for microcontrollers. For reliability, the operation of the three cores is locked together with ODRG [7] into a TCLS configuration. In this default soft-error tolerant mode, the three cores all receive identical inputs, and their outputs are majority-voted, thereby emulating a single, reliable core to the programmer and the system.…”

Section: Soc Architecturementioning

confidence: 99%

“…It includes three Ibex [6] processing cores, by default, operating together in a triple-core lockstep (TCLS) mode. Using on-demand redundancy grouping (ODRG) [7], these cores can be unlocked to increase performance when reliability is not required. Furthermore, the memory is protected with an efficient error correction code (ECC), and scrubbers are added to correct latent errors.…”

Section: Introductionmentioning

confidence: 99%

Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm

Rogenmoser,

Benini

2023

2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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One of the key challenges when operating microcontrollers in harsh environments such as space is radiationinduced single event upsets (SEUs), which can lead to errors in computation. Common countermeasures rely on proprietary radiation-hardened technologies, low density technologies, or extensive replication, leading to high costs and low performance and efficiency. To combat this, we present Trikarenos, a faulttolerant 32-bit RISC-V microcontroller SoC in an advanced TSMC 28nm technology. Trikarenos alleviates the replication cost by employing a configurable triple-core lockstep configuration, allowing three Ibex cores to execute applications reliably, operating on ECC-protected memory. If reliability is not needed for a given application, the cores can operate independently in parallel for higher performance and efficiency. Trikarenos consumes 15.7 mW at 250 MHz executing a fault-tolerant matrixmatrix multiplication, a 21.5x efficiency gain over state-of-the-art, and performance is increased by 2.96x when reliability is not needed for processing, with a 2.36x increase in energy efficiency.

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“…In this paper, we introduce a space-ready multi-core RISC-V-based computing system featuring a Hybrid Modular Redundancy (HMR) approach. We leverage the independent cores available in a multi-core RISC-V cluster for redundant execution in a dynamically runtime configurable manner and introduce Dual-Core Lockstep (DCLS) and Triple-Core Lockstep (TCLS) modes, extending the On-Demand Redundancy Grouping with TCLS configurable under reset presented in [37]. Our design allows each application to configure its reliability setting according to its requirements, possibly decided at runtime.…”

Section: Introductionmentioning

confidence: 99%

Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space

Rogenmoser¹,

Tortorella²,

Rossi³

et al. 2023

Preprint

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Space Cyber-Physical Systems (S-CPS) such as spacecraft and satellites strongly rely on the reliability of onboard computers to guarantee the success of their missions. Relying solely on radiation-hardened technologies is extremely expensive, and developing inflexible architectural and microarchitectural modifications to introduce modular redundancy within a system leads to significant area increase and performance degradation as well. To mitigate the overheads of traditional radiation hardening and modular redundancy approaches, we present a novel Hybrid Modular Redundancy (HMR) approach, a redundancy scheme that features a cluster of RISC-V processors with a flexible on-demand dual-core and triple-core lockstep grouping of computing cores with runtime split-lock capabilities. Further, we propose two recovery approaches, software-based and hardware-based, trading off performance and area overhead. Running at 430 MHz, our fault-tolerant cluster achieves up to 1160 MOPS on a matrix multiplication benchmark when configured in non-redundant mode and 617 and 414 MOPS in dual and triple mode, respectively. A software-based recovery in triple mode requires 363 clock cycles and occupies 0.612 mm 2 , representing a 1.3% area overhead over a non-redundant 12-core RISC-V cluster. As a high-performance alternative, a new hardware-based method provides rapid fault recovery in just 24 clock cycles and occupies 0.660 mm 2 , namely ∼9.4% area overhead over the baseline non-redundant RISC-V cluster. The cluster is also enhanced with split-lock capabilities to enter one of the available redundant modes with minimum performance loss, allowing execution of a safety-critical portion of code with 310 and 23 clock cycles overhead for entry and exit, respectively. The proposed system is the first to integrate these functionalities on an open-source RISC-V-based compute device, enabling finely tunable reliability vs. performance trade-offs.

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On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster

Cited by 9 publications

References 10 publications

PULP Fiction No More—Dependable PULP Systems for Space

PULP Fiction No More—Dependable PULP Systems for Space

Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm

Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space

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