On determining sensitization criterion in an iterative gate sizing process

In the last step of the design flow, circuit In section 2, this coefficient based approach is described. performance optimization is a difficult task to realize. The goalIn section 3, we present the coefficient definition and of this work is to avoid the use of CPU time expensive random evaluation. In sections 4 and 5, we validate and compare, mathematical methods, by defining an accurate and respectively, the proposed approach on full ISCAS'85 by deterministic circuit sizing protocol, allowing easy and fast comparing the performance of different ISCAS benchmarks sizing of circuits at the required speed. We propose a sized with an industrial tool or with our prototype using the coefficient based approach to solve the divergence branch coefficient based approach. Finally we conclude in section 4.problem for circuit sizing. Validation is given by comparing, in a standard 180nm CMOS process, the performance of different II. DESCRIPTION OF THE COEFFICIENT BASED APPROACHISCAS benchmarks sized with an industrial tool and following our methodology.This approach consists in determining a coefficient (y)for each input of divergence branch encountered on the

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On determining sensitization criterion in an iterative gate sizing process

Cited by 4 publications

References 9 publications

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