On Developing One-Chip Integration of 1.2 kV SiC MOSFET and JBS Diode (JBSFET)

2021

Self Cite

A 27 nm gate oxide thickness has been successfully used for manufacturing high performance 650V 4H-SiC planargate, inversion-channel power JBSFETs in a 6-inch commercial foundry with three (Linear, Hexagonal, and Octagonal) cell topologies. The 27 nm gate oxide thickness allows operation of these JBSFETs at a gate bias of 15 V compared with 20 V used in previous reports for devices with 55 nm gate oxide thickness. The width for the Schottky contact was varied to optimize the performance of the JBS diode in the third quadrant for each cell topology. An on-state voltage drop of 2.5 V or less was achieved in the third quadrant for all the cell topologies by current flow through the integrated JBS diode, satisfying the objective of effectively bypassing the MOSFET body diode. The best breakdown voltage was achieved using the Octagonal cell topology with a half-cell Schottky contact width of 1.1 m. It had a breakdown voltage of 850 V with a low leakage current of less than 5 nA at 650 V. The Linear cell (with half-cell Schottky contact width of 1.0 m) and the Octagonal cell (with half-cell Schottky contact width of 2.8 m) had blocking voltages of 800 V. The hexagonal cell topology (with half-cell Schottky contact width of 1.5 m) had the worst blocking voltage of 715 V. Numerical simulation results are provided to show that the leakage current in all cell topologies begins to increase when the electric field at the Schottky contact exceeds 1.5 MV/cm. The lowest specific on-resistance was obtained with the hexagonal cell topology but its gate-drain charge was 2x larger than the conventional Linear cell design. The Octagonal cell topology with half-cell Schottky contact width of 1.1 m had the same specific on-resistance as the Linear cell case with 2x smaller gate-drain charge. This work demonstrates for the first time that excellent High-Frequency Figures-of-Merit can be achieved with a reduced gate drive voltage of 15 V for 650 V SiC JBSFETs by using a smaller gate oxide thickness of 27 nm and the Octagonal cell topology.

mentioning

confidence: 99%

Assessment of Linear, Hexagonal, and Octagonal Cell Topologies for 650 V 4H-SiC Inversion-Channel Planar-Gate Power JBSFETs Fabricated With 27 nm Gate Oxide Thickness

Agarwal

Han

2021

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“…The process for making the SiC JBSFETs has been previously described in detail [6] [7]. In this case, an opening is made to the middle of the polysilicon gate window where the N + source and P + shielding regions are excluded as shown in Fig.…”

Section: Manufacturing Processmentioning

confidence: 99%

“…The JBS diode and MOSFET structures discussed in the previous sections have been integrated into a single monolithic device called the JBSFET [6] [7]. The JBSFET cross-section, shown in Fig.…”

Section: Power Jbsfetsmentioning

confidence: 99%

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Third Generation PRESiCE™ Technology for Manufacturing SiC Power Devices in a 6-Inch Commercial Foundry

2020

A third-generation PRESiCE TM technology has been qualified for manufacturing SiC power devices in a commercial foundry using 6 inch wafers. JBS diodes, power MOSFETs, and JBSFETs with 1.2 kV ratings were fabricated using this technology with good yields. Conventional device structures similar to commercially available products were used in this work to perform the process qualification. Extensive measurements on devices from three process qualification lots demonstrate excellent parametric distributions within a wafer, between wafers within a lot, and between wafers from the three lots. The electrical characteristics of the JBS diodes, power MOSFETs and JBSFETs manufactured with PRESiCE TM are similar to those of commercial products.

“…Integration of the SiC JBS diode inside the 1.2 kV SiC planargate linear-cell MOSFET chip created the first JBSFET structure [14]. The net SiC chip area and manufacturing cost was reduced with this approach because the space taken by the edge termination for the separate JBS diode is eliminated [15].…”

Section: Introductionmentioning

confidence: 99%

2.3 kV 4H-SiC Planar-Gate Accumulation Channel Power JBSFETs: Analysis of Experimental Data

Agarwal

2021

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Experimental results obtained for 2.3 kV SiC planargate power JBSFETs with different cell topologies are analyzed in this paper using analytical models and numerical simulations. All the accumulation-channel devices were simultaneously manufactured in a 6-inch commercial foundry with channel length of 0.5 µm and gate oxide thickness of 55 nm. The Schottky contact width was chosen to achieve an on-state voltage drop of below 2.8 V in the 3 rd quadrant for the integrated JBS diodes. Lower specific on-resistance of the Hexagonal and higher values for the Octagonal cell topologies compared with the conventional Linear cell design were experimentally observed. New analytical models developed for the various cell topologies reveal that these differences arise from changes in the relative contributions from the N + source contact, channel, and accumulation region resistances. The analysis reported in this paper provides new insight on the importance of the accumulation layer resistance to the Octagonal cell topology. Numerical simulation reveal that the measured leakage current behavior correlates with the electric field observed at the Schottky contact within the 2.3 kV JBSFET cell structures. The leakage current begins to rise rapidly when the electric field exceeds 1.5 MV/cm due to Schottky barrier lowering and enhanced tunneling. The reverse transfer capacitance and gate charge were found to correlate with the JFET region density within the different cell topologies. The measured on-state voltage drop in the third quadrant was found to correlate with the JBS diode density in the cell topologies. A new high-frequency figure-of-merit [Vf3Q*Qgd,sp] is proposed for SiC JBSFETs. The Octagonal cell designs are found to be the most suitable for high frequency applications of 2.3 kV JBSFETs based on the HF-FOMs [Ron*Qgd] and [Vf3Q*Qgd,sp].