On effective and efficient in-field TSV repair for stacked 3D ICs

Abstract

Three-dimensional (3D) integration based on through-silicon-vias (TSVs) is rapidly gaining traction for industry adoption. However, manufacturing processes for TSVs have been shown to introduce new failure mechanisms. In particular, thermo-mechanical stress and electromigration introduce reliability threats for TSVs, e.g., voids and interfacial cracks, which can lead to hard-to-predict timing errors on critical paths with TSVs, thereby resulting in accelerated chip failure in the field. Burn-in for screening latent defects during manufacturing is expensive and its effectiveness for new TSV defect types has yet to be thoroughly characterized. We describe a reconfigurable in-field repair solution that is able to effectively tolerate latent TSV defects through the judicious use of spares. The proposed solution includes a reconfigurable repair architecture that enables spare TSV sharing between TSV grids, and the corresponding in-field repair algorithms. The effectiveness and efficiency of our proposed solution is evaluated using 3D benchmark designs.

Dynamic Self-Repair Architectures for Defective Through-silicon Vias

“…The X-axis and Y-axis show different TSV repair approaches, and threshold voltage variations normalized by the proposed method, respectively. The proposed method shows the least impact on the transistors by the TSV channels, and an NoC-type architecture [6] shows the highest stress on the transistors caused by adjacent TSVs. Table 1 shows various aspects of TSV repair methods.…”

“…If m spare TSVs are used, the spares can be re-routed up to m defective TSV channels. Figure 2(b) shows a TSV repair architecture based on a switch and routing path such as a Network-on-Chip (NoC) [6]. It allows for fully defective TSV channel replacement by spare TSVs using minimum routing paths.…”

“…In this paper, unlike conventional repair approaches [1], [3], [6]- [7], [14], we minimize the use of logic around the TSVs owing to the stress and reliability issues addressed in Functional values section III. Based on this guideline, we propose a dynamic hardware-mapping based failing TSV repair architecture.…”

“…After packaging, the packaged product is tested as a final test. Some researches have been conducted on built-in-self-test (BIST) approaches to enhance a test flow for TSV technologies [2]- [6], [12], [13].…”

“…In 3D SICs, spare TSVs, such as column or row redundancies in memory, can be mainly used as a hardware redundancy technique to repair defective TSVs between stacked dies. Previous researches have focused on hardware-redundancy based TSV repair approaches [1], [3], [6]- [7], [14]. In this paper, we propose a new BIST feature to identify defective TSVs in 3D SICs and introduce costeffective dynamic TSV repair techniques.…”