On error-correction performance and implementation of polar code list decoders for 5G

Abstract

Polar codes are a class of capacity achieving error correcting codes that has been recently selected for the next generation of wireless communication standards (5G). Polar code decoding algorithms have evolved in various directions, striking different balances between error-correction performance, speed and complexity. Successive-cancellation list (SCL) and its incarnations constitute a powerful, well-studied set of algorithms, in constant improvement. At the same time, different implementation approaches provide a wide range of area occupations and latency results. 5G puts a focus on improved error-correction performance, high throughput and low power consumption: a comprehensive study considering all these metrics is currently lacking in literature. In this work, we evaluate SCL-based decoding algorithms in terms of error-correction performance and compare them to low-density parity-check (LDPC) codes. Moreover, we consider various decoder implementations, for both polar and LDPC codes, and compare their area occupation and power and energy consumption when targeting short code lengths and rates. Our work shows that among SCL-based decoders, the partitioned SCL (PSCL) provides the lowest area occupation and power consumption, whereas fast simplified SCL (Fast-SSCL) yields the lowest energy consumption. Compared to LDPC decoder architectures, different SCL implementations occupy up to 17.1× less area, dissipate up to 7.35× less power, and up to 26× less energy.

An Experimental Demonstration of Rate-Adaptation Using Shaped Polar Codes for Flexible Optical Networks

“…It can be seen from Fig. 7, that the IPPC scheme with shaping recovers the puncturing loss and provides an increase 16 18 20 of 200 km of distance for η = 4.5 to η = 6 compared to the EPPC scheme at the same data rate. It can also be observed that the error-free distance of IPPC scheme for η = 4 is increased by 400 km over the EPPC scheme.…”

“…It is also proven that the successive cancellation (SC) decoder for polar codes does not display an error floor [15], as compared to LDPC codes which display an error floor if they are not carefully designed for each SE [9]. Hardware based polar decoders of short code lengths are already under investigation for 5G [16], [17] due to their ability to achieve Gbps throughput at less area, power and energy consumption than the WiMAX LDPC codes [16]. As a potential candidate for future lightwave systems, the performance of SC polar decoder was compared with state-ofthe-art spatially coupled LDPC codes in [18].…”

Memory Management in Successive-Cancellation based Decoders for Multi-Kernel Polar Codes

“…While software guarantees a higher degree of flexibility in terms of data structures, fast software decoders have to rely on efficient memory management [5], [6]. The importance of smart memory usage is even more evident in hardware implementations, where memory accounts for the majority of area occupation and power consumption, and heavily impacts decoder speed [7]- [9]. The memory structure first proposed in [10] for purely binary polar codes, and widely adopted in SC-based decoders [11], relies on the observation that memory requirements decrease as the decoding stage increases.…”

Efficient Log Likelihood Ratio Estimation for Polar Codes

“…In order to reduce latency and increase throughput, Simplified SCL (SSCL) [7,8] and Fast-SSCL decoding algorithms were proposed, that guarantee significant reduction in the number of required time-steps with respect to SCL without relying on approximations or code specific design. The partitioned SCL (PSCL) algorithm in [9,10] breaks the code into constituent codes (partitions) and each constituent code is decoded with the SCL algorithm.…”

“…SCL-based decoders are currently one of the best candidates to meet 5G error-correction performance requirements and throughput. An FPGA implementation of SC-based decoding algorithm was able to achieve an information throughput of 1 Gbps at a clock frequency of 106 MHz [10,14]. A double-column 1024-parallel architecture of belief propagation (BP) polar decoder enables a 4.68 Gbps throughput at a clock frequency of 300 MHz [15].…”