On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method

Rastogi, Ashesh; Chen, Wei; Kundu, Sandip

doi:10.1109/dac.2007.375256

Cited by 5 publications

(6 citation statements)

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“…Another source of error can be the interaction between the leakage current of different gates [23,24]. This interaction is known as loading effect.…”

Section: Analysis Of Methods Accuracymentioning

confidence: 99%

Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits

Butzen

Rosa

Filho

et al. 2010

Microelectronics Journal

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Leakage currents are gaining importance as design parameters in nanometer CMOS technologies. A novel leakage current estimation method, which takes into account the dependency of leakage mechanisms, is proposed for general CMOS complex gates, including non-series-parallel transistor arrangements, not covered by existing approaches. The main contribution of this work is a fast, accurate, and systematic procedure to determine the potentials at transistor network nodes for calculating standby static currents. The proposed method has been validated through electrical simulations, showing an error smaller than 7% and an 80 Â speed-up when comparing to electrical simulation.

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“…Another source of error can be the interaction between the leakage current of different gates [23,24]. This interaction is known as loading effect.…”

Section: Analysis Of Methods Accuracymentioning

confidence: 99%

Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits

Butzen

Rosa

Filho

et al. 2010

Microelectronics Journal

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“…BTBT current includes the phonons distribution of the electrons, and it occurs when the bandgap voltage is less than the voltage drop across the p junction. Many works of literature treat the problem of expressing this type of leakage starting from calculating the I BTBT current density [9,10], more details regarding the BTBT current could be found in [11,12] 2317 the source and drain is larger than the substrate voltage, an amount of current will flow through the drain/source-substrate junction. The sum of these two junctions flowing current represents the total MOSFET BTBT leakage current is shown in the following formula [16].…”

Section: Modeling Of Band To Band Tunnelingmentioning

confidence: 99%

“…Udit Monga and others [7] proposed a model for subthreshold current in short channel effect and double-gate MOSFET by assuming that the electrostatic fields are dominated by the coupling capacitances, J. P. Sun [8] proposed a model for gate current and capacitance for CMOS device in the nanoscale paradigm considering the full consistent solution for Schrodinger-Passion Equation, a unified and accurate study for the gate structure to model its current and capacitance. A. Rastogi and his team in [9] proposed a model for total leakage at Sub-Micron paradigm with the inclusion of some of its sources such as the sub-threshold leakage and Band-To-Band Tunneling (BTBT). However, with the scaling down of the device dimensions, other types of leakage will be dominant and need to be modeled.…”

Section: Introductionmentioning

confidence: 99%

Accurate leakage current models for MOSFET nanoscale devices

Rjoub¹,

Mistarihi²,

Taradeh³

2020

IJECE

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This paper underlines a closed forms of MOSFET transistor’sleakage current mechanisms inthe sub 100nmparadigm.The incorporation of draininduced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (Isub) wasinvestigated in detail. The Band-To-Band Tunneling (IBTBT) due to the source and Drain PN reverse junction were also modeled witha close and accurate model using a rectangularapproximation method (RJA). The three types of gate leakage (IG) were also modeled and analyzed for parasitic (IGO), inversion channel (IGC), and gate substrate (IGB).In addition, the leakage resources due to the aggressive reduction in the oxide thickness (<5nm) have been investigated. Simulation results using HSPICEexhibits a tremendous agreement with the BSIM4 model. The dominant value of the sub-threshold leakage was due to the DIBL and GIDL effects. Various recommendations regarding minimizing the leakage current at both device level and the circuit level were suggested at the end of this paper

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“…In this mode the inputs of the gate at logic '1' or '0' are of interest. However the loading effect [11] requires leakage to be calculated not only for 0 and V DD values of output voltage but also for values around them. Hence we develop a continuous model for all values of voltages.…”

Section: Leakagementioning

confidence: 99%

Finite-Point Gate Model for Fast Timing and Power Analysis

Ganesan

Mitev

Wang

et al. 2008

9th International Symposium on Quality Electronic Design (Isqed 2008)

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This paper proposes a new finite-point based approach for efficient characterization of CMOS gate. The new method identifies several key points on the I-V and Q-V curves to define the behavior of the static CMOS gate. It targets performance metrics such as timing, short-circuit power and leakage in the presence of process variations. Experimental results validate the accuracy of the new approach and yields simulation speeds more than 15X faster than BSIM based library characterization.

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On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method

Cited by 5 publications

References 0 publications

Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits

Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits

Accurate leakage current models for MOSFET nanoscale devices

Finite-Point Gate Model for Fast Timing and Power Analysis

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