On flash A/D-converters with low-precision comparators

Frey, Matthias; Loeliger, Hans-Andrea

doi:10.1109/iscas.2006.1693487

Cited by 6 publications

(9 citation statements)

References 11 publications

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“…These quantities do not appear to make sense for ADCs that are corrected according to (2). However, it is obvious from Fig.…”

Section: Issues With Adc Correctionmentioning

confidence: 92%

“…However, in this paper, we allow arbitrary thresholds; we only assume that the thresholds are ordered (or reordered, if necessary) such that for . If the analog input lies in bin , i.e., if , the standard (uncorrected) digital output is (1) while the corrected digital output is (2) the mean of the corresponding bin (see Fig. 1).…”

Section: Flash Adcs With Low-precision Comparatorsmentioning

confidence: 99%

“…The digital correction amounts to reordering the thresholds such that holds and then to use (2). (Thresholds outside the allowed interval are simply discarded.)…”

Section: Flash Adcs With Low-precision Comparatorsmentioning

confidence: 99%

“…While such an approach to ADCs has been suggested by several authors (as will be detailed below), its attractivity for current steering DACs does not seem to have been noticed in the literature. This paper is semi-tutorial in that most of its substance was presented in [1] and [2]. However, the analytical results given in the Appendix are new.…”

Section: Introductionmentioning

confidence: 99%

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On the Static Resolution of Digitally Corrected Analog-to-Digital and Digital-to-Analog Converters With Low-Precision Components

Frey

Loeliger

2007

IEEE Trans. Circuits Syst. I

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Abstract-This semi-tutorial paper considers the effect of component mismatch on the static accuracy of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) with digital correction. First, it is noted that the effective static resolution of flash ADCs is not much reduced by component mismatch: with proper digital correction, the loss due to mismatch is only about 1.3 bit, virtually independently of the mismatch level unless the mismatch is very small. Second, it is noted that current steering DACs may actually benefit from component mismatch. Moreover, with proper digital correction, current steering DACs can achieve an effective static resolution of bits with as few as +2 near-unit low-precision current sources.Index Terms-Analog-to-digital converter (ADC), calibration, digital-to-analog converter (DAC).

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“…These quantities do not appear to make sense for ADCs that are corrected according to (2). However, it is obvious from Fig.…”

Section: Issues With Adc Correctionmentioning

confidence: 92%

Section: Flash Adcs With Low-precision Comparatorsmentioning

confidence: 99%

“…The digital correction amounts to reordering the thresholds such that holds and then to use (2). (Thresholds outside the allowed interval are simply discarded.)…”

Section: Flash Adcs With Low-precision Comparatorsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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On the Static Resolution of Digitally Corrected Analog-to-Digital and Digital-to-Analog Converters With Low-Precision Components

Frey

Loeliger

2007

IEEE Trans. Circuits Syst. I

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“…These results present a difficulty that must be overcome, but one that can be overcome with future design effort. For example, increases in comparator mismatch and its effects on ADC accuracy are another major concern for feature scaling, but recent work (such as [16]) offer (partial) solutions to this problem.…”

Section: Limitations Of Studymentioning

confidence: 99%

An Examination of the Effect of Feature Size Scaling on Effective Power Consumption in Analog to Digital Converters

Boyle

Kilambi

Długosz

et al. 2006

2006 IEEE Workshop on Signal Processing Systems Design and Implementation

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-Wireless Sensor Network (WSN) nodes require components with ultra-low power consumption, as they must operate without an external power supply. One technique for reducing consumption of a system is to scale it to a smaller technology; however, in recent technologies is not clear whether the decrease in dynamic power consumption outweighs the increase in static power consumption (due to leakage currents). Here this is considered by examining the power consumption of three implementations of an analog to digital converter (ADC). One in 350 nm, one in 180 nm, and one in 90 nm, were simulated and compared. The results show that the dynamic power consumption was reduced by a factor of four over the three technologies, but standby power consumption increased by an order of magnitude. The power consumption of the 180 nm implementation was always lower than the 350 nm implementation. However, assuming a WSN application with a duty cycle of 1%, the effective power consumption of the 90 nm ADC was higher than both the 180 nm and the 350 nm implementation. This highlights the dominance of leakage current in determining the effective power consumption in lowthroughput nodes.

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A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC

Bichan

Dunwell

Wang

et al. 2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper analyzes the impact of clock skew between comparators in a flash ADC, showing that the SNDR penalty introduced by this effect can become significant at high frequencies. To address this issue, a passive resonant clock network is proposed to distribute the clock to the comparators in a flash ADC. The inductive termination of this network serves to resonate out the parasitic and input capacitances of the ADC, allowing for a 2.5-GHz clock signal to be conveyed to a load of 256 comparators while consuming less power than traditional clock networks due to the reduced number of active clock buffers required. This clock network produces little timing skew at the resonant frequency, thereby obviating the need for a track-andhold amplifier, which further reduces the power requirements of the ADC. This clock network was implemented in a 5-bit flash ADC designed in 65 nm CMOS, with a measured SNDR of 26 dB.

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On flash A/D-converters with low-precision comparators

Cited by 6 publications

References 11 publications

On the Static Resolution of Digitally Corrected Analog-to-Digital and Digital-to-Analog Converters With Low-Precision Components

On the Static Resolution of Digitally Corrected Analog-to-Digital and Digital-to-Analog Converters With Low-Precision Components

An Examination of the Effect of Feature Size Scaling on Effective Power Consumption in Analog to Digital Converters

A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC

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