On Hard Adders and Carry Chains in FPGAs

Luu, Jason; McCullough, Conor; Wang, Sen; Huda, Safeen; Yan, Bo; Chiasson, Charles; Kent, Kenneth B.; Anderson, Jason; Rose, Jonathan; Betz, Vaughn

doi:10.1109/fccm.2014.25

Cited by 19 publications

(9 citation statements)

References 15 publications

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“…We argue that this is not the best approach to discover carry chains: mainly, (1) it is impossible to discover chains in circuits where adders are implemented at the gate level, (2) misses opportunities of using full adders or small-bitwidth adders in other situations not immediately derived from explicit additions, and (3) removes these components from the sight of logic synthesis, thus preventing even some basic logic optimisations such as constant propagation. Instantiating hardened adders before logic optimisation may easily lead to redundant or unnecessary logic not being eliminated [6]. Additionally, in the VTR flow, (4) the adders presented as black boxes prevent the synthesizer ABC from correctly modelling the critical path of the circuit.…”

Section: B Discovering Carry Chainsmentioning

confidence: 99%

“…Additionally, suboptimal mapping decision can be made by assigning adders to carry chains before technology mapping (i.e., design step that transforms the gate-level description of the input into a network of LUTs). Luu et al [6] have recently shown that using carry chains provides an average speed up of approximately 15% for an area penalty of approximately 5%. However, in some benchmarks using carry chains led to slower and bigger circuits.…”

Section: Introductionmentioning

confidence: 99%

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Improved carry chain mapping for the VTR flow

Petkovska

Zgheib

Novo

et al. 2015

2015 International Conference on Field Programmable Technology (FPT)

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Carry chains facilitate the implementation of adders and improve the performance of arithmetic circuits in FPGAs. The last version of the commonly used open-source Verilog-toRouting (VTR) CAD flow now enables modelling carry chains in FPGA architectures. However, one of the shortcomings of the existing flow lies in its inability to identify arithmetic operations when described as gate-level circuits. Moreover, the VTR flow squanders most of the LUTs preceding the chain logic. This paper focuses on these two problems and proposes preprocessing the circuit before technology mapping to allow for a more efficient use of carry chains. The first proposed method maps logic on the carry chains for circuits expressed using a gate-level description. On average, it identifies about 30% more meaningful full adders than the existing tool flow operating on the RTL descriptions. Area is thus improved by up to 15% with an average of 6% for almost no delay penalty. Secondly, we increase the use of the LUTs preceding the chain logic by a factor 2 on average. This reduces delay (up to 9%) and area (up to 2%), compared to the existing VTR flow. The new approach is independent of the specific carry-chain architecture and can be generically adapted to any FPGA with built-in hardened adders.

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Section: B Discovering Carry Chainsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Improved carry chain mapping for the VTR flow

Petkovska

Zgheib

Novo

et al. 2015

2015 International Conference on Field Programmable Technology (FPT)

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“…Columns of CLBs are replaced by heterogeneous blocks such as memory banks and digital signal processing (DSP) blocks. BLEs comprise of fracturable LUTs [25] and hard carry chains [26]. Local routing architecture also interconnects adjacent CLBs to provide highways between neighbors [27], [28].…”

Section: A Island-style Fpga Fabricmentioning

confidence: 99%

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Tang

Giacomin

Micheli

et al. 2019

IEEE Trans. VLSI Syst.

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In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can automatically generate Verilog and SPICE netlists based on realistic FPGA configurations and a high-level eTtensible Markup Language-based FPGA architectural description language. The outputted Verilog netlists can be used to generate layouts of full FPGA fabrics through a semicustom design flow. SPICE simulation decks can be generated at three levels of complexity, namely, full-chip-level, gridlevel, and component-level, providing different tradeoff between accuracy and simulation time. In order to enable such level of analysis, we presented two SPICE netlist partitioning techniques: loads extraction and parasitic net activity estimation. Electrical simulations showed that averaged over the selected benchmarks, the grid-/component-level approach can achieve 6.1×/7.5× execution speed-up with 9.9%/8.3% accuracy loss, respectively, compared to the full-chip level simulation. FPGA-SPICE was showcased through three different case studies: 1) an area breakdown analysis for static random access memory-based FPGAs, showing that configuration memories are a dominant factor; 2) a power breakdown comparison to analytical models, analyzing the source of accuracy loss; and 3) a robustness evaluation against process corners, studying their impact on energy consumption of full FPGA fabrics.

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“…In this work, we prototype our technique focusing on the adder compound operator. Luu et al explored using hardened adders in VTR to improve efficiency of arithmetic operations as they are a rather small and prevalent circuit [10]. In that work, the authors measured an overall performance improvement of 15%.…”

Section: Related Workmentioning

confidence: 99%

Towards Trainable Synthesis for Optimized Circuit Deployment on FPGA

Legault

Patros

Kent

2018

2018 International Symposium on Rapid System Prototyping (RSP)

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Field Programmable Gate Arrays (FPGAs) utilize multiple programmable elements and non-programmable blocks. After synthesizing an input Hardware Design Language (HDL) design into a circuit, optimizations are used to discover a satisfactory deployment on a target FPGA. HDLs' compound operations, such as addition, can be implemented in various ways and thus, multiple but functionally equivalent circuits can be synthesized. To leverage this, we propose a methodology that first enables configurable synthesis of compound operations. Second, it trains the system using a set of HDL files and architectures to optimize target performance objectives, such as critical path length and power. We prototyped our technique in the open source Verilog-To-Routing (VTR) tool. We subsequently produced two configuration files targeting different deployment objectives; experimental results with the VTR Verilog benchmarks revealed significant improvements. Index Terms-FPGA, HDL, compound arithmetic operators, reconfigurable synthesis, Verilog-To-Routing • We evaluate our technique using five search sets targeting different performance metrics. Measurements revealed significant performance improvements. II. BACKGROUND Verilog is an HDL used to design, model and validate electronic systems [1]. Verilog-to-Routing (VTR) is set of CAD tools that perform synthesis, optimization, verification,

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On Hard Adders and Carry Chains in FPGAs

Cited by 19 publications

References 15 publications

Improved carry chain mapping for the VTR flow

Improved carry chain mapping for the VTR flow

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Towards Trainable Synthesis for Optimized Circuit Deployment on FPGA

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