The upcoming adoption of low-voltage-ride-through requirements in low-voltage distribution systems is expected to raise significant challenges in the operation of grid-tied inverters. Typically, these inverters interconnect photovoltaic units, which are the predominant distributed energy resource in low-voltage distribution networks, under an umbrella of standards and protection schemes. As such, a challenging issue that should be considered in low-voltage distribution network applications, regards the coordination between the line protection scheme (typically consisting of a non-settable fuse) and the low-voltage-ride-through operation of photovoltaic generators. During a fault, the fuse protecting a low-voltage feeder may melt, letting the generator to continue its ride-through operation. Considering that the efficacy/speed of the anti-islanding detection is affected by ride-through requirements, this situation can lead to protracted energization of the isolated feeder after fuse melting (unintentional islanding). To address this issue, this paper proposes a fault-current-limitation based solution, which does not require any modification in the existing protection scheme. The operation principles, design, and implementation of this solution are presented, while, its effectiveness is supported by extensive simulations in a test-case low-voltage distribution system. A discussion on the presented results concludes the paper.2 of 20 under consideration [1,3]. LV distribution networks are expected to be dominated by inverter-interfaced DG-units (IIDGs), principally photovoltaic ones [1,4]. To this end, several inverter-design concepts have been proposed, aiming at the compliance of LV-IIDGs with LVRT requirements [5][6][7].Since LVRT requirements keep DG-units connected to the network during faults, they contradict the requirement for a quick anti-islanding detection. Indeed, despite the fact that several efficient passive [8], active [9][10][11][12], or other hybrid methods [13] have been proposed over the last years for fast anti-islanding detection, their cooperation with LVRT operation remains a challenging issue under research, especially under high DG-penetration conditions. The authors of [14] attempted to clarify this contradiction, by allowing a PV-unit to trip without complying with LVRT, if passive anti-islanding detection asserts. This approach is also recommended within IEEE 1547-2018 [2]. Although the anti-islanding detection is decoupled by LVRT operation in those cases, the adoption of LVRT requirements can affect its efficacy/speed. For example, LVRT affects any anti-islanding method that is based on the magnitude of grid-tied voltage. Compromising the anti-islanding detection is an issue of concern to DSOs and power system engineers [15,16]. This problem is further intensified when frequency disturbance ride through requirements are also adopted (e.g., low/high-frequency ride-through, rate-of-change-of-frequency ride-through, and voltage-phase-angle-changes ride-through [2]). Within this context, i...