On Improving the Security of Logic Locking

Yasin, Muhammad; Rajendran, Jeyavijayan; Sinanoglu, Ozgur; Karri, Ramesh

doi:10.1109/tcad.2015.2511144

Cited by 279 publications

(179 citation statements)

References 28 publications

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“…For robust logic obfuscation, the key-related gate-bits are injected in a certain way into the design that causes the key information extraction process to be hard to achieve [22]. Yasin et al improved on the work through inserting more pairwise keys [5]. In [23], IC protection is done by insertion of process variation (PV) sensors inside the design at specific selected nodes along with generation of a unique key for each IC.…”

Section: Prior Workmentioning

confidence: 99%

“…Even though the design of ICs has become very widespread, only a few countries (e.g., the USA and Japan) have a rigorous set of rules and regulations to prevent IC piracy from exposing or stealing electronic products [5][6][7][8][9]. A report from Information Handling Services (IHS) company in the USA showed that the untrusted ICs and the counterfeited chips have increased four-fold since 2009 [10].…”

Section: Introductionmentioning

confidence: 99%

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E2LEMI:Energy-Efficient Logic Encryption Using Multiplexer Insertion

Alasad

Yuan

2017

Electronics

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Due to the outsourcing of chip manufacturing, countermeasures against Integrated Circuit (IC) piracy, reverse engineering, IC overbuilding and hardware Trojans (HTs) become a hot research topic. To protect an IC from these attacks, logic encryption techniques have been considered as a low-cost defense mechanism. In this paper, our proposal is to insert the multiplexer (MUX) with two cases: (i) we randomly insert MUXs equal to half of the output bit number (half MUX insertions); and (ii) we insert MUXs equal to the number of output bits (full MUX insertions). Hamming distance is adopted as a security evaluation. We also measure the delay, power and area overheads with the proposed technique.

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Section: Prior Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

E2LEMI:Energy-Efficient Logic Encryption Using Multiplexer Insertion

Alasad

Yuan

2017

Electronics

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“…In general, sensitization attacks use automatic test pattern generation (ATPG) tools to propagate the key-bits to the primary outputs of the encrypted design, while SAT attacks [23] can decrypt the locked circuit and reveal its secret key. A technique [24], namely strong logic locking (SLL) [24], was proposed to prevent propagating key-bits based attacks by inserting each two pairs of key-gates to a gate in the original circuit. They also incorporated Advanced Encryption Standard (AES) cryptography to prevent SAT attacks.…”

Section: Prior Workmentioning

confidence: 99%

“…Figure 9 shows the more resilient techniques against SAT-attack that we discuss in detail. Instead of directly connecting all of the key-bits to the key-gates in a locked circuit, some of the key-bits are fed as inputs to 32-bit AES cryptography [24]. Then, the outputs of AES are considered as the actual part of the key-bits, as illustrated in Figure 9a.…”

Section: Sat Based Attackmentioning

confidence: 99%

“…Since the complexity of the design becomes very large and needs different types of equipment as well as fabricating process involvement [24], many companies design the ICs and then fabricate them at other companies. Thus, ICs might be imitated by the untrusted company so the company could sell them in the markets illegally or insert a Trojan inside the chips [38].…”

Section: Testing In An Untrusted Foundrymentioning

confidence: 99%

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Logic Locking Using Hybrid CMOS and Emerging SiNW FETs

Alasad

Yuan

2017

Electronics

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Abstract:The outsourcing of integrated circuit (IC) fabrication services to overseas manufacturing foundry has raised security and privacy concerns with regard to intellectual property (IP) protection as well as the integrity maintenance of the fabricated chips. One way to protect ICs from malicious attacks is to encrypt and obfuscate the IP design by incorporating additional key gates, namely logic encryption or logic locking. The state-of-the-art logic encryption techniques certainly incur considerable performance overhead upon the genuine IP design. The focus of this paper is to leverage the unique property of emerging transistor technology on reducing the performance overhead as well as preserving the robustness of logic locking technique. We design the polymorphic logic gate using silicon nanowire field effect transistors (SiNW FETs) to replace the conventional Exclusive-OR (XOR)-based logic cone. We then evaluate the proposed technique based on security metric and performance overhead.

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Hardware obfuscation of AES IP core using combinational hardware Trojan circuit for secure data transmission in IoT applications

Chhabra

Lata

2022

Concurrency and Computation

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In semiconductor industry, reusability-based System-on-Chip architecture using hardware intellectual property (IP) cores play a prominent role in Internet-of-Things (IoT) applications for secure data transmission. The advent of IoT makes it possible for physical things to transmit, process, compute, and receive data over internet. But, it also introduces in-device communication security vulnerabilities. Advanced Encryption Standard (AES) IP has been used to address security vulnerabilities in IoT. It is an efficient and high-performance crypto algorithm used in IoT devices for secure and fast data encryption. However, due to rise of many attacks, the security of AES IP is also under threat. Hardware obfuscation is one such prominent countermeasure that mitigates hardware attacks such as tampering, reverse engineering, and malicious alteration. This article presents secure AES IP mechanism using the potential technique of obfuscation inspired by the concept of combinational hardware Trojan. Experimental results show that the proposed technique is resilient against reverse-engineering, malicious alteration, Boolean satisfiability attack, and key-sensitizing attacks. The confusion and diffusion features of obfuscated AES IP are higher in terms of Hamming distance, avalanche effect, and balance rate. The proposed technique is implemented in Basys-3 FPGAs within 5% of power and area overhead while maintaining high throughput.

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On Improving the Security of Logic Locking

Cited by 279 publications

References 28 publications

E2LEMI:Energy-Efficient Logic Encryption Using Multiplexer Insertion

E2LEMI:Energy-Efficient Logic Encryption Using Multiplexer Insertion

Logic Locking Using Hybrid CMOS and Emerging SiNW FETs

Hardware obfuscation of AES IP core using combinational hardware Trojan circuit for secure data transmission in IoT applications

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