On learning-based methods for design-space exploration with high-level synthesis

Liu, Hung‐Yi; Carloni, Luca P.

doi:10.1145/2463209.2488795

Cited by 159 publications

(84 citation statements)

References 13 publications

(40 reference statements)

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“…Consequently, it only takes 7 mins to enumerate the full design space with Aladdin compared to 52 hours with the RTL flow. The HLS RTL generation time per design is comparable to that reported by other researchers [39].…”

Section: Algorithm-to-solution Timesupporting

confidence: 81%

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures

Shao¹,

Reagen²,

Wei³

et al. 2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

121

117

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Hardware specialization, in the form of accelerators that provide custom datapath and control for specific algorithms and applications, promises impressive performance and energy advantages compared to traditional architectures. Current research in accelerator analysis relies on RTL-based synthesis flows to produce accurate timing, power, and area estimates. Such techniques not only require significant effort and expertise but are also slow and tedious to use, making large design space exploration infeasible. To overcome this problem, we present Aladdin, a pre-RTL, power-performance accelerator modeling framework and demonstrate its application to system-on-chip (SoC) simulation. Aladdin estimates performance, power, and area of accelerators within 0.9%, 4.9%, and 6.6% with respect to RTL implementations. Integrated with architecture-level core and memory hierarchy simulators, Aladdin provides researchers an approach to model the power and performance of accelerators in an SoC environment.

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Section: Algorithm-to-solution Timesupporting

confidence: 81%

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures

Shao¹,

Reagen²,

Wei³

et al. 2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

121

117

View full text Add to dashboard Cite

show abstract

“…Moreover, in order to measure the quality of an approximate Pareto-optimal curve, we borrow the metric of average distance from reference set (ADRS) utilized by [13] [20]. In our case, we consider a two-objectives (Initiation Interval II vs. area A) DSE problem.…”

Section: B Experimental Resultsmentioning

confidence: 99%

“…In terms of II, the best design point on the Paretooptimal curve with dataflow is 30% better than that without dataflow. However, the current DSE techniques using HLS tools [2][3] [17] [20][27] primarily focus on optimizing individual loops and ignore the dataflow feature between loops. Table I presents the detailed II results for a subspace of the entire design space.…”

Section: A Motivating Examplementioning

confidence: 99%

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Design space exploration of multiple loops on FPGAs using high level synthesis

Zhong

Venkataramani

Liang

et al. 2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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Abstract-Real-world applications such as image processing, signal processing, and others often contain a sequence of computation intensive kernels, each represented in the form of a nested loop. High-level synthesis (HLS) enables efficient hardware implementation of these loops using high-level programming languages. HLS tools also allow the designers to evaluate design choices with different trade-offs through pragmas/directives. Prior design space exploration techniques for HLS primarily focus on either single nested loop or multiple loops without consideration to the data dependencies among them. In this paper, we propose efficient design space exploration techniques for applications that consist of multiple nested loops with or without data dependencies. In particular, we develop an algorithm to derive the Paretooptimal curve (performance versus area) of the application when mapped onto FPGAs using HLS. Our algorithm is efficient as it effectively prunes the dominated points in the design space. We also develop accurate performance and area models to assist the design space exploration process. Experiments on various scientific kernels and real-world applications demonstrate that our design space exploration technique is accurate and efficient.

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“…In [6] [9] [5] different approaches are taken to integrate specialized functional units of various granularity directly into a general purpose core. In [3] [8] [7] accelerators are considered as SoC components where data must be offloaded to the accelerator's own memory before the computation can begin. We refer to these types of accelerators as tightly-and loosely-coupled respectively [2].…”

Section: Related Workmentioning

confidence: 99%

Quantifying acceleration: Power/performance trade-offs of application kernels in hardware

Reagen

Shao

Wei

et al. 2013

International Symposium on Low Power Electronics and Design (ISLPED)

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Abstract-As the traditional performance gains of technology scaling diminish, one of the most promising directions is building special purpose fixed function hardware blocks, commonly referred to as accelerators. Accelerators have become prevalent in industrial SoC designs for their low power, high performance potential. In this work we explore thousands of implementations of classical software workloads in hardware. This thorough, detailed design space search of hardware accelerators gives architects a quantitative way to reason about the differences in implementations. The exploration presented in this work shows that the space is full of poor design choices. By thoroughly analyzing each benchmark, we show which provide the most performance when implemented in hardware given a fixed power budget and explain which design techniques work best for each workload.

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On learning-based methods for design-space exploration with high-level synthesis

Cited by 159 publications

References 13 publications

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures

Design space exploration of multiple loops on FPGAs using high level synthesis

Quantifying acceleration: Power/performance trade-offs of application kernels in hardware

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