On-line software-based self-test of the Address Calculation Unit in RISC processors

Abstract

Software-based Self-Test (SBST) can be used during the mission phase of microprocessor-based systems to periodically assess the hardware integrity. However, several constraints are imposed to this approach, due to the coexistence of test programs with the mission application. This paper proposes a method for the generation of SBST programs to test on-line the Address Calculation Unit of embedded RISC processors, which is one of the most heavily impacted by the online constraints. The proposed strategy achieves high stuck-at fault coverage on both a MIPS-like processor and an industrial 32-bit pipelined processor; these two case studies show the effectiveness of the technique and the low effort.

On the in-field functional testing of decode units in pipelined RISC processors

“…A signature can be implemented by coupling together memory instructions in order to excite and observe the faults : for examp le, a Store operation into a certain memo ry address can be followed by a Load instruction using the same location. An effective approach to test the operands consists in expressing the memory location differently in the two operations [14], as in figure 5.…”

Stochastic testing of processing cores in a many-core architecture

“…Additionally, SBST techniques remove the over-testing problem associated with nonfunctional testing techniques and can be re-used for online periodic testing of processors. Many research groups have worked on SBST of single core processors [23][24][25][26][27][28][29]. Today SBST is a mature technique for testing simple microprocessors and is an integral part of the manufacturing test process for single core processors [27].…”

A Flexible Framework for the Automatic Generation of SBST Programs

“…For example, a constraint could require to only apply valid instructions. Especially when targeting in-field SBST, restrictive constraints are imposed, e.g., the memory area available for the test code and data may be limited [20], some input signals may hardly be controllable (e.g., reset), and only the final content of the memory can be observed. Hence, the generation of the corresponding test program is significantly more complex than for end-of-manufacturing test.…”