On minimization of test power through modified scan flip-flop

Ahlawat, Satyadev; Tudu, Jaynarayan

doi:10.1109/isvdat.2016.8064878

Cited by 4 publications

(4 citation statements)

References 25 publications

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“…Tables 1 and 2 provides their classification based on the common principle being used. [9]- [13]. They block the functional output going to the combinational logic during test mode, thereby reducing redundant switching during shifting.…”

Section: Classificationmentioning

confidence: 99%

“…Figure 1(a) shows a cell that uses separate latches, while the cell in Figure 1(b) uses gated control signals to block toggling. The scan cells in [12], [13] additionally retain the last capture value. They preserve the combinational logic state when the cell changes mode from functional to shift, which helps to reorder patterns effectively for minimizing power.…”

Section: Classificationmentioning

confidence: 99%

“…Figure 1. Scan cells with gated functional output during shifting, (a) cell with separate latches for functional and scan path [13] and (b) trimodal scan cell [11] The cell in [9] removes the slave part in a conventional scan cell. Also, its scan path sees two fewer inverters and one less transmission gate.…”

Section: Classificationmentioning

confidence: 99%

“…SA in the scan cell is minimized during shift operation due to the reduced number of cells on the scan path. The cell in [13] 3405 logic driven by the cell during shifting and reducing toggles in the cell itself. Furthermore, the cell retains captured value after changing to shift mode, a valuable property for pattern reordering.…”

Section: Classificationmentioning

confidence: 99%

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Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

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While power reduction during testing is necessary for today's low-power devices, it also lowers test costs. Scan-based methods are the most widely used approach for testing integrated circuits (IC). Test vectors are shifted into and out of scan chains bit by bit during shift operation. The time required for shift operation dominates the test time. With the geometries shrinking (7 nm→5 nm→3 nm→1.8 nm), ICs are required to be tested for newer defects, increasing test time. The most effective way to reduce test time for scan operation is to increase the frequency of the shift operation. Reduction in shift power enables scan operation to be performed with increased frequency, reducing test time, and test cost. This paper presents a survey of techniques proposed recently for shift power reduction. Various techniques, including special flip-flop usage, segmentation, reordering, and low-pass filter, are being reviewed. The techniques are organized based on main attributes to underscore their similarities and differences. Pros and cons in terms of complexities involved in their implementation are discussed. We believe this paper will provide a point of reference for further studies in scan shift power reduction and will be helpful to both industry and academia.

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Section: Classificationmentioning

confidence: 99%

Section: Classificationmentioning

confidence: 99%