On producing exactly rounded results in digit-serial on-line arithmetic

Parhami, Behrooz

doi:10.1109/acssc.2000.910641

Search citation statements

Order By: Relevance

Paper Sections

Select...

Floating-point Arithmetic1

Citation Types

Supporting

Mentioning

Contrasting

Publication Types

Select...

Article1

Relationship

Self Cite1

Independent0

Authors

Journals

Cited by 1 publication

(1 citation statement)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The advantages above are not limited to bit-parallel arithmetic. In a companion paper [13], the author has shown how the use of DLSB representation solves one of the problems Fig. 7 Graphical representation of precision extension and alignment preshift for DLSB numbers in pipelined, digit -serial arithmetic.…”

Section: Floating-point Arithmeticmentioning

confidence: 99%

Double-least-significant-bits 2's-complement number representation scheme with bitwise complementation and symmetric range

Parhami

2008

IET Circuits Devices Syst.

Self Cite

View full text Add to dashboard Cite

A scheme is proposed for representing 2's-complement binary numbers in which there are two least-significant bits (LSBs). Benefits of the extra LSB include making the number representation range symmetric (i.e. from 22 k21 to 2 k21 for k-bit integers), allowing sign change by simple bitwise logical inversion, facilitating multiprecision arithmetic and enabling the truncation of results in lieu of rounding. These advantages justify the added storage and interconnect costs stemming from the extra bit. Operation latencies show little or no change relative to conventional 2's-complement arithmetic, thus making double-LSB representation attractive.

show abstract

Section: Floating-point Arithmeticmentioning

confidence: 99%