On Random Wiring in Practicable Folded Clos Networks for Modern Datacenters

Camarero, Cristóbal; Martínez, Carmen; Beivide, Ramón

doi:10.1109/tpds.2018.2805344

Cited by 5 publications

(5 citation statements)

References 36 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this section, we evaluate FlowLever using a realistic flow trace extracted from the core networks public data centers. To accommodate the increasing network speed among heterogeneous devices, such as intra-data-center networks [32], WANs [31], 5G [33], etc., we simulate a workload by replaying the real-world flow dataset in a speed-up and repeated fashion. Two experiments are conducted on FlowLever.…”

Section: Macro Benchmarksmentioning

confidence: 99%

FlowLever: Leverage Flow Director for Packet Dispatch Acceleration in NFV

Fu,

Zhang,

Zhang

et al. 2024

IEEE Access

View full text Add to dashboard Cite

The efficiency of dispatching incoming network flow packets to the destination virtual network function (VNF) has been recognized as a key problem in network function virtualization (NFV) platforms. Recent hardware assisted packet dispatch systems tend to rely on expensive software-defined network (SDN) switches or SmartNICs to mitigate the dispatch performance bottleneck, commonly observed in traditional software dispatch systems. In this paper, we revisit a hardware Flow Director (FDir) feature commonly found on commercial off-the-shelf NICs and propose a FDir-based NFV system that greatly accelerates packet dispatch with a much lower total cost of ownership (TCO). FlowLever is carefully designed to resolve nontrivial challenges such as the lack of flow state monitoring in FDir, the limited flow classification schema, heavy flow cache reconfiguration overhead, and high VNF scaling costs. With our softwarehardware codesigned dispatch system and newly proposed flow activeness detection and cache replacement mechanisms, our evaluation using real-world network traffic traces shows that FlowLever improves the throughput by 1.6x -2.8x and costs only 0.2 ms -0.6 ms for load balance during VNF scaling.

show abstract

Section: Macro Benchmarksmentioning

confidence: 99%

FlowLever: Leverage Flow Director for Packet Dispatch Acceleration in NFV

Fu,

Zhang,

Zhang

et al. 2024

IEEE Access

View full text Add to dashboard Cite

show abstract

“…Because our motivation to reduce the cost of the network via bandwidth tapering is only possible in a hierarchical network, we choose a fat tree, originally proposed as a folded Clos [27], to represent a popular hierarchical topology. Fat trees and their variants are extensively used in datacenters [21,22,83] and HPC [10,45,49,77] due to their favorable wiring properties and their ability to provide full throughput for any traffic pattern, assuming perfect load balancing and full bisection bandwidth (i.e., the higher layers of the fat tree have the same total bandwidth as the lower layers) [43]. A recent example in HPC is the HyperX topology that is similar to a fat tree [10].…”

Section: The Promise Of Silicon Photonics For Reconfigurabilitymentioning

confidence: 99%

“…This motivates us to choose a hierarchical topology that allows us to pursue our goal, and in particular a fat tree as a representative hierarchical topology. Fat trees and their variants are extensively used in datacenters [21,22] and HPC [10,45,49,77] due to the favorable wiring properties and their ability to handle any traffic pattern with full bisection bandwidth assuming perfect load balance [43]. Furthermore.…”

Section: Related Workmentioning

confidence: 99%

“…In this paper, we propose to use silicon photonic (SiP) switches as circuit-switched components between electronic packet switches (EPSs) in order to dynamically adjust the connectivity (steer bandwidth) between the ToR (first-level) and aggregation (second-level) EPSs of a three-level fat tree topology. Fat trees and their variants such as HyperX are extensively used in datacenters [21,22] and HPC [10,45,49,77]. Our goal is to optimally adjust the connectivity of the lower layers of the network to minimize the number of packets that traverse the higher layers, while avoiding to divide the network into disjoint electrical and optical parts [11].…”

mentioning

confidence: 99%

See 1 more Smart Citation

Bandwidth steering in HPC using silicon nanophotonics

Shen

Teh

Meng

et al. 2019

Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis

View full text Add to dashboard Cite

As bytes-per-FLOP ratios continue to decline, communication is becoming a bottleneck for performance scaling. This paper describes bandwidth steering in HPC using emerging reconfigurable silicon photonic switches. We demonstrate that placing photonics in the lower layers of a hierarchical topology efficiently changes the connectivity and consequently allows operators to recover from system fragmentation that is otherwise hard to mitigate using common task placement strategies. Bandwidth steering enables efficient utilization of the higher layers of the topology and reduces cost with no performance penalties. In our simulations with a few thousand network endpoints, bandwidth steering reduces static power consumption per unit throughput by 36% and dynamic power consumption by 14% compared to a reference fat tree topology. Such improvements magnify as we taper the bandwidth of the upper network layer. In our hardware testbed, bandwidth steering improves total application execution time by 69%, unaffected by bandwidth tapering.

show abstract

“…In [3] and [2] randomized versions of folded Clos networks were introduced. These topologies are more scalable, allow for easy upgrades of the system and entail less cost.…”

Section: Introductionmentioning

confidence: 99%