On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques

Abstract

With the advancement of VLSI manufacturing technology, entire electronic systems can be implemented in a single integrated circuit. Due to the complexity in SoC design, circuit testability becomes one of the most challenging works. Without careful planning in Design For Testability (DFT) design, circuits consume more power in test mode operation than that in normal functional mode. This elevated testing power may cause problems including overall yield lost and instant circuit damage. In this paper, we present two approaches to minimize scan based DFT power dissipation. First methodology includes routing cost consideration in scan chain reordering after cell placement, while second methodology provides test pattern compression for lower power. We formulate the first problem as a Traveling Salesman Problem (TSP), with different cost evaluation from [18], [19], and apply an efficient heuristic to solve it. In the second problem, we provide a selective scan chain architecture and perform a simple yet effective encoding scheme for lower scan testing power dissipation. The experimental results of ISCAS'89 benchmarks show that the first methodology obtains up to 10% average power saving under the same low routing cost compared with a recent result in [19]. The second methodology reduces over 17% of test power compared with filling all don't care (X) bit with 0 in one of ISCAS'89 benchmarks. We also provide the integration flow of these two approaches in this paper.