On-Resistance Degradation Induced by Hot-Carrier Injection in LDMOS Transistors With STI in the Drift Region

Chen, J.F.; Tian, Kuen-Shiuan; Chen, Shiang-Yu; Wu, K.; Liu, C.M.

doi:10.1109/led.2008.2001969

Cited by 74 publications

(17 citation statements)

References 29 publications

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“…However, in repetitive avalanche applications, other potential failure mechanisms are introduced as avalanche pulses, although within the MOSFET SOA, repetitively dissipate power through the MOSFET. Hot-carrier injection (HCI) into the gate dielectric is a well known short-channel effect in deep submicrometer complementary metal oxide on semiconductor (CMOS) technology [11,12] as well as power MOSFETs [13][14][15].…”

Section: Introductionmentioning

confidence: 99%

The Impact of Repetitive Unclamped Inductive Switching on the Electrical Parameters of Low-Voltage Trench Power nMOSFETs

Alatise

Kennedy

Petkos

et al. 2010

IEEE Trans. Electron Devices

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Section: Introductionmentioning

confidence: 99%

The Impact of Repetitive Unclamped Inductive Switching on the Electrical Parameters of Low-Voltage Trench Power nMOSFETs

Alatise

Kennedy

Petkos

et al. 2010

IEEE Trans. Electron Devices

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“…Hot carrier degradation in such STI-based devices was reported in [30]. The devices studied here form a complementary pair of nLDMOS and pLDMOS with maximum operation voltages of 60 V. In Fig.…”

Section: Hot Carrier Degradation In Ldmosmentioning

confidence: 89%

Reliability Simulation Models for Hot Carrier Degradation

Scholten

Vries

Bisschop

et al. 2014

Hot Carrier Degradation in Semiconductor Devices

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Because reliability considerations are gradually shifting from device to circuit level (Groeseneken et al., Trends and perspectives for electrical characterization and reliability assessment in advanced CMOS technologies, Proceedings of the ESSDERC, 2010, pp. 64-72), circuit reliability simulation is becoming increasingly important. To enable reliability simulation, reliability simulation models are a prerequisite. These simulation models are often based on analytical descriptions taken from the literature. Apart from the desire to make these models fit experimental data accurately, one encounters some specific practical problems when building them. These problems include (1) the translation from equations derived for DC stress conditions to equations valid under more general transient stress conditions, (2) the translation of the degradation of observables to the degradation of compact model parameters, and (3) the need to keep the simulation overhead of these models to the bare minimum. These issues will be addressed in this chapter, and illustrated using the examples of (1) reverse-V BE degradation in HBTs, (2) hot-carrier degradation in MOSFETs, and (3) hot-carrier degradation in LDMOS devices.

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“…The extended drain structure with isolation either by STI or Thermo-oxide and "RESURF" technology [1] are widely used to obtain high-voltage capability while keeping low on resistance so to optimize the specific resistance versus breakdown voltage trade-off. In past, a rugged LDMOS for a 0.35μm Linear BiCMOS technology, which achieves a strongly enhanced electrical SOA, has been presented [2][3]. A buried body implant was added to suppress the parasitic bipolar transistor; hence no snapback was observed in the I-V characteristics: this important feature enables an extension of the current curves to higher drain voltages, when impact ionization at the drain side of the drift region becomes dominant.…”

Section: Introductionmentioning

confidence: 99%

“…Thus, an unusual current "enhancement" is reported at large gate voltages with a subsequent saturation of the current at high drain biases. High operational drain and gate biases make the LDMOS device vulnerable to the damage caused by hot-carrier injection (HCI), and the reliability characterization in STI based LDMOS devices have recently drawn much attention [2][3][4][5][6]. However, very little is known on the hotcarrier injection effects in the rugged LDMOS device when it is operated in the high impact-ionization regime.…”

Section: Introductionmentioning

confidence: 99%

Study of impact of LATID on HCI reliability for LDMOS devices

Sheu

Yang

Chien

et al. 2016

MATEC Web of Conferences

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Abstract. This paper demonstrates electrical degradation due to Hot Carrier Injection (HCI) stress for nLDMOS devices with different Large Angle Tilted Implantation Doping (LATID) techniques for p-body. It seems that optimization of the device with LATID angle for p-body in nLDMOS is important to achieve improved HCI performance and observed that HCI degradation is minimum for 30 0 LATID for p-body. We observed Si/SiO2 interface trap under various stress conditions, were evaluation based on our Sentaurus simulation, and we compare trapped charge density and distribution for various LATID angles and it was less for 30 0 tilt. Trap-related models were employed to perform Ron and Id,sat degradations during the HCI stress test. So nLDMOS device with 30 0 tilt angle for p-body shows better HCI performance compared to other LATID. Also our new proposed device structure shows less HCI degradations when compared with silicon data of HCI degradations for other nLDMOS structure.

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On-Resistance Degradation Induced by Hot-Carrier Injection in LDMOS Transistors With STI in the Drift Region

Cited by 74 publications

References 29 publications

The Impact of Repetitive Unclamped Inductive Switching on the Electrical Parameters of Low-Voltage Trench Power nMOSFETs

The Impact of Repetitive Unclamped Inductive Switching on the Electrical Parameters of Low-Voltage Trench Power nMOSFETs

Reliability Simulation Models for Hot Carrier Degradation

Study of impact of LATID on HCI reliability for LDMOS devices

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