On synthesis of speed-independent circuits at STG level

Lin, Kuan-Jen; Kuo, Chi-Wen

doi:10.1109/aspdac.1997.600345

Search citation statements

Order By: Relevance

Paper Sections

Select...

Logic Synthesis1

Citation Types

Supporting

Mentioning

Contrasting

Publication Types

Select...

Other1

Relationship

Self Cite0

Independent1

Authors

Journals

Cited by 1 publication

(1 citation statement)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Logic synthesis methodology mainly employs Petri Net (PN) [62] to describe async circuits, also known as the graph-based methodology. The system specification is usually specified in Signal Transition Graph (STG) [63]. Graph specification is not straightforward to recognize the functionality of system, error prone and difficult to debug, so for complex system, it is too large and tedious to manage.…”

Section: Logic Synthesismentioning

confidence: 99%

Design methodologies for robust and low-overhead asynchronous quasi-delay-insensitive digital systems

Zhou¹

View full text Add to dashboard Cite

In the past decades of electronic circuit designs, the synchronous-logic (sync) is the main de-facto design approach for digital systems. This is largely due to its synchronization to a global clock signal (or its variants thereof) which simplifies the data transfer. Nevertheless, designing digital circuits and systems based on sync approach is becoming more challenging due to the increase in process, voltage and temperature (PVT) variations in the deep submicron fabrication process. An alternative design approach which is based on the asynchronous-logic (async), is

show abstract

Section: Logic Synthesismentioning

confidence: 99%

Design methodologies for robust and low-overhead asynchronous quasi-delay-insensitive digital systems

Zhou¹

View full text Add to dashboard Cite

show abstract

On synthesis of speed-independent circuits at STG level

Cited by 1 publication

References 12 publications

Design methodologies for robust and low-overhead asynchronous quasi-delay-insensitive digital systems

Design methodologies for robust and low-overhead asynchronous quasi-delay-insensitive digital systems

Contact Info

Product

Resources

About