On the asymptotic costs of multiplexer-based reconfigurability

York, Johnathan; Chiou, Derek

doi:10.1145/2228360.2228503

Cited by 2 publications

(2 citation statements)

References 31 publications

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“…A special care has to be taken in designing of an accelerator that is capable of attaining desired performance while maintaining generality of the accelerator in also supporting other operations in the domain of DLA computations. Coarse-grained Reconfigurable Architectures (CGRAs) are a good candidate for the domain of DLA computations since they are capable of attaining performance of Application Specific Integrated Circuits (ASICs) while flexibility of Field Programmable Gate Arrays (FPGAs) [8][9] [10]. Recently, there have been several proposals in the literature in developing BLAS and LAPACK on custamizable CGRA platforms through algorithm-architecture co-design where macro operations in the operations pertaining to DLA computations are identified and realized on a Reconfigurable Data-path (RDP) that is tightly coupled to the processor pipeline [11][12].…”

Section: Introductionmentioning

confidence: 99%

Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization

Merchant

Vatwani

Chattopadhyay

et al. 2018

IEEE Trans. Parallel Distrib. Syst.

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We present efficient realization of Generalized Givens Rotation (GGR) based QR factorization that achieves 3-100x better performance in terms of Gflops/watt over state-of-the-art realizations on multicore, and General Purpose Graphics Processing Units (GPGPUs). GGR is an improvement over classical Givens Rotation (GR) operation that can annihilate multiple elements of rows and columns of an input matrix simultaneously. GGR takes 33% lesser multiplications compared to GR. For custom implementation of GGR, we identify macro operations in GGR and realize them on a Reconfigurable Data-path (RDP) tightly coupled to pipeline of a Processing Element (PE). In PE, GGR attains speed-up of 1.1x over Modified Householder Transform (MHT) presented in the literature. For parallel realization of GGR, we use REDEFINE, a scalable massively parallel Coarse-grained Reconfigurable Architecture, and show that the speed-up attained is commensurate with the hardware resources in REDEFINE. GGR also outperforms General Matrix Multiplication (gemm) by 10% in-terms of Gflops/watt which is counter-intuitive.Index Terms-Parallel computing, orthogonal transforms, dense linear algebra, multiprocessor system-on-chip, instruction level parallelism ! Ranjani Narayan has over 15 years experience at IISc and 9 years at Hewlett Packard. She has vast work experience in a variety of fields computer architecture, operating systems, and special purpose systems. She has also worked in the Technical University of Delft, The Netherlands, and Massachusetts Institute of Technology, Cambridge, USA. During her tenure at HP, she worked on various areas in operating systems and hardware monitoring and diagnostics systems. She has numerous research publications.She is currently Chief Technology Officer at Morphing Machines he was the chief engineer at the Embedded Systems chair at TU Dortmund. In 2002, he joined RWTH Aachen University as a professor for Software for Systems on Silicon. His research comprises software development tools, processor architectures, and system-level electronic design automation, with focus on application-specific multicore systems. He published numerous books and technical papers and served in committees of the leading international EDA conferences. He received various scientific awards, including Best Paper Awards at DAC and twice at DATE, as well as several industrial awards. Dr. Leupers is also engaged as an entrepreneur and in turning novel technologies into innovations. He holds several patents on system-on-chip design technologies and has been a co-founder of LISATek (now with Synopsys), Silexica, and Secure Elements. He has served as consultant for various companies, as an expert for the European Commission, and in the management boards of large-scale projects like HiPEAC and UMIC. He is the coordinator of EU projects TETRACOM and TETRAMAX on academia/industry technology transfer.

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Section: Introductionmentioning

confidence: 99%

Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization

Merchant

Vatwani

Chattopadhyay

et al. 2018

IEEE Trans. Parallel Distrib. Syst.

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“…Recently, Coarse-grained Reconfigurable Architectures (CGRAs) have gained popularity due to their power performance and flexibility [5][6] [7]. Performance advantage in CGRAs is attained by supporting selected number of data-paths out of all possible data-paths and hence they occupy middle ground between Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs) [8] [9][10] [11]. CGRAs like REDEFINE have special feature that they can be customized for application domains where several data-paths belonging to a particular domain of interest are realized as a reconfigurable ASIC [12].…”

Section: Introductionmentioning

confidence: 99%

Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design

Merchant,

Vatwani,

Chattopadhyay

et al. 2016

Preprint

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Basic Linear Algebra Subprograms (BLAS) play key role in high performance and scientific computing applications. Experimentally, yesteryear multicore and General Purpose Graphics Processing Units (GPGPUs) are capable of achieving up to 15 to 57% of the theoretical peak performance at 65W to 240W respectively for compute bound operations like Double/Single Precision General Matrix Multiplication (XGEMM). For bandwidth bound operations like Single/Double precision Matrix-vector Multiplication (XGEMV) the performance is merely 5 to 7% of the theoretical peak performance in multicores and GPGPUs respectively. Achieving performance in BLAS requires moving away from conventional wisdom and evolving towards customized accelerator tailored for BLAS through algorithm-architecture co-design. In this paper, we present acceleration of Level-1 (vector operations), Level-2 (matrix-vector operations), and Level-3 (matrix-matrix operations) BLAS through algorithm architecture co-design on a Coarse-grained Reconfigurable Architecture (CGRA). We choose REDEFINE CGRA as a platform for our experiments since REDEFINE can be adapted to support domain of interest through tailor-made Custom Function Units (CFUs). For efficient sequential realization of BLAS, we present design of a Processing Element (PE) and perform micro-architectural enhancements in the PE to achieve up-to 74% of the theoretical peak performance of PE in DGEMM, 40% in DGEMV and 20% in double precision inner product (DDOT). We attach this PE to REDEFINE CGRA as a CFU and show the scalability of our solution. Finally, we show performance improvement of 3-140x in PE over commercially available Intel micro-architectures, ClearSpeed CSX700, FPGA, and Nvidia GPGPUs.

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On the asymptotic costs of multiplexer-based reconfigurability

Cited by 2 publications

References 31 publications

Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization

Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization

Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design

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