On the BCJR trellis for linear block codes

McEliece, Robert J.

doi:10.1109/18.508834

Cited by 195 publications

(157 citation statements)

References 27 publications

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“…Finding a trellis with minimal complexity (i.e., minimal number of edges as explained in [33]) is a rather complex task and is out of the scope of this tutorial paper.…”

Section: Siso Relationships On Trellisesmentioning

confidence: 99%

Iterative Decoding of Concatenated Convolutional Codes: Implementation Issues

2007

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This tutorial paper gives an overview of the implementation aspects related to turbo decoders, where the term turbo generally refers to iterative decoders intended for Parallel Concatenated Convolutional Codes as well as for Serial Concatenated Convolutional Codes. We start by considering the general structure of iterative decoders, and the main features of the SISO algorithm that forms the heart of iterative decoders. Then, we show that very efficient parallel architectures are available for all types of turbo decoders allowing high speed implementations. Other implementation aspects like quantization issues and stopping rules used in conjunction with buffering for increasing throughput are considered. Finally, we perform an evaluation of the complexities of the turbo decoders as a function of the main parameters of the code.

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“…Finding a trellis with minimal complexity (i.e., minimal number of edges as explained in [33]) is a rather complex task and is out of the scope of this tutorial paper.…”

Section: Siso Relationships On Trellisesmentioning

confidence: 99%

Iterative Decoding of Concatenated Convolutional Codes: Implementation Issues

2007

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“…The decoder used in each case is the standard belief-propation algorithm with maximum a posteriori decoding at each VN and CN (see a decription for the G-LDPC case in [12]). Thus, for the Hamming constraint nodes, soft-outputs are computed using a BCJR decoder [27] working on the BCJR trellis [27], [28] of the component code.…”

Section: ) G-ldpc Code Family C Iimentioning

confidence: 99%

Quasi-Cyclic Generalized LDPC Codes With Low Error Floors

Liva¹,

Ryan²,

Chiani³

2007

IEEE Trans. Commun.

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Abstract-In this paper, a novel methodology for designing structured generalized LDPC (G-LDPC) codes is presented. The proposed design results in quasi-cyclic G-LDPC codes for which efficient encoding is feasible through shift-register-based circuits. The structure imposed on the bipartite graphs, together with the choice of simple component codes, leads to a class of codes suitable for fast iterative decoding. A pragmatic approach to the construction of G-LDPC codes is proposed. The approach is based on the substitution of check nodes in the protograph of a low-density parity-check code with stronger nodes based, for instance, on Hamming codes. Such a design approach, which we call LDPC code doping, leads to low-rate quasi-cyclic G-LDPC codes with excellent performance in both the error floor and waterfall regions on the additive white Gaussian noise channel.

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“…We use a locally optimal decoder which employs the BCJR algorithm designed to the "BCJR trellis" [28] [29] for the linear code represented by the GCP. We allow both SPCs and GCPs to co-exist in the generalized Tanner graph, i.e., some of the SPCs are not combined to form a GCP.…”

Section: Generalized-ldpc Decodermentioning

confidence: 99%

LDPC decoder strategies for achieving low error floors

Han

Ryan

2008

2008 Information Theory and Applications Workshop

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Abstract-One of the most significant impediments to the use of LDPC codes in many communication and storage systems is the error-rate floor phenomenon associated with their iterative decoders. The error floor has been attributed to certain subgraphs of an LDPC code's Tanner graph induced by so-called trapping sets. We show in this paper that once we identify the trapping sets of an LDPC code of interest, a sum-product algorithm (SPA) decoder can be custom-designed to yield floors that are orders of magnitude lower than the conventional SPA decoder. We present three classes of such decoders: (1) a bi-mode decoder, (2) a bit-pinning decoder which utilizes one or more outer algebraic codes, and (3) three generalized-LDPC decoders. We demonstrate the effectiveness of these decoders for two codes, the rate-1/2 (2640,1320) Margulis code which is notorious for its floors and a rate-0.3 (640,192) quasi-cyclic code which has been devised for this study. Although the paper focuses on these two codes, the decoder design techniques presented are fully generalizable to any LDPC code.

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On the BCJR trellis for linear block codes

Cited by 195 publications

References 27 publications

Iterative Decoding of Concatenated Convolutional Codes: Implementation Issues

Iterative Decoding of Concatenated Convolutional Codes: Implementation Issues

Quasi-Cyclic Generalized LDPC Codes With Low Error Floors

LDPC decoder strategies for achieving low error floors

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