On the conception and analysis of a 12-GHz push-push phase-locked DRO

Gravel, Jean-Francois; Wight, J.S.

doi:10.1109/tmtt.2005.860508

Cited by 34 publications

(21 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…2, the fundamental suppression is 35.12 dBc. The fundamental suppression is better than that in [1][2][3]. Fig.…”

mentioning

confidence: 78%

“…Introduction: For low phase noise applications, such as satellite communication and radar, it is desirable to phase lock the free running push-push dielectric resonator oscillator (DRO) [1][2][3] to a high stable crystal oscillator for further improving the phase noise. The phaselocking can be implemented at f 0 , or at 2f 0 .…”

mentioning

confidence: 99%

“…The phaselocking can be implemented at f 0 , or at 2f 0 . In [3], a push-push PLDRO is designed by locking the 2f 0 . However, the use of a high frequency prescaler increases the cost and power consumption of the system.…”

mentioning

confidence: 99%

See 2 more Smart Citations

Fundamental wave phase-locked dual-band push-push DRO using out-of-phase Wilkinson power combiner

Cao

Tang

2010

Electron. Lett.

View full text Add to dashboard Cite

A new push-push phase-locked dielectric resonator oscillator (PLDRO) with dual-band (C/Ku) output capability is presented. An out-of-phase Wilkinson power combiner is used to provide the fundamental ( f 0 ) output. The phase-locking is implemented at f 0 as an alternative to direct locking the push-push output frequency (2f 0 ) using prescalers. The push-push PLDRO has shown a fundamental suppression of 35.12 dBc and a second-harmonic suppression of 34.77 dBc at the 2f 0 output and the f 0 output, respectively. Experimental results also indicate a maximum spur level of 277.4 dBc, and phase noise values of 2109.6 and 2143 dBc/Hz at 10 kHz and 1 MHz offsets, respectively, from a 12.6 GHz carrier.Introduction: For low phase noise applications, such as satellite communication and radar, it is desirable to phase lock the free running push-push dielectric resonator oscillator (DRO) [1-3] to a high stable crystal oscillator for further improving the phase noise. The phaselocking can be implemented at f 0 , or at 2f 0 . In [3], a push-push PLDRO is designed by locking the 2f 0 . However, the use of a high frequency prescaler increases the cost and power consumption of the system. Lee et al.[4] designed a 60 GHz planar-type push-push VCO with an integrated frequency divider working near 30 GHz. As a result, a 60 GHz frequency synthesiser can be realised by locking relative lower frequencies. Besides the phase noise considerations, next generation wireless systems, such as multimode transreceivers and cognitive radios, require the push-push DRO to have dual-band output capability.Thus, the f 0 signal should also be coupled out at the condition that the fundamental suppression and phase noise of the 2f 0 output are not deteriorated. Moreover, the output power of the f 0 signal should be sufficient for local oscillator applications.This Letter introduces a new push-push PLDRO. Compared with conventional designs, it provides not only the 2f 0 signal but also the f 0 signal by using an out-of-phase Wilkinson power combiner. Furthermore, as the phase-locking is implemented at the fundamental frequency, the increased phase detector gain helps reduce the risk of locking failures and phase noise. The concept proposed here can also be applied to millimetre-wave PLDRO designs where phase-locking becomes more difficult.

show abstract

“…2, the fundamental suppression is 35.12 dBc. The fundamental suppression is better than that in [1][2][3]. Fig.…”

mentioning

confidence: 78%

mentioning

confidence: 99%

See 1 more Smart Citation

Fundamental wave phase-locked dual-band push-push DRO using out-of-phase Wilkinson power combiner

Cao

Tang

2010

Electron. Lett.

View full text Add to dashboard Cite

show abstract

“…Because the technology of W-band signal source is relatively mature [4][5][6][7], this section will especially introduce the terahertz tripler, which is a technical difficulty in the chain. Moreover, the LO source introduced in this article is aimed to work for three months as part of radiometer front-end carried by satellite.…”

Section: Design and Measurementmentioning

confidence: 99%

Design of a 212 GHZ Lo Source Used in the Terahertz Radiometer Front-End

Jin¹,

Zhang²,

Jiang³

et al. 2017

PIER Letters

View full text Add to dashboard Cite

Abstract-We introduce a 212 GHz LO source which could be used to drive sub-harmonic mixer in the radiometer front-end. It mainly includes a phase-locked dielectric resonator, a 71 GHz power source and a 212 GHz tripler. Actually, design of 212 GHz tripler is the key technology in the LO chain because the research on W band source is relatively mature. Based on our former research work, there is a great improvement in the design of 212 GHz tripler. At room temperature, the measured efficiency is more than 9% in 208 ∼ 218 GHz, and the maximum efficiency is about 14.5% at 215.5 GHz when being driven with 21.8 dBm of input power. Besides demand on the main technical specifications, the stability of each module is also extremely important since the front-end is designed to keep working for three months.

show abstract

“…The conventional PLDRO uses a reference crystal oscillator and a SPD, which compares the harmonic frequency of the reference and the feedback signal from VCDRO to generate an error signal for the loop filter [6]. As a variation, the fundamental VCDRO is replaced with a push-push VCDRO [7,8], and the SPD is replaced with a mixer [8]. However, the aforementioned PLDROs have the same limit: the output frequency must be an integer multiple of the reference frequency, typically 100 MHz.…”

Section: Introductionmentioning

confidence: 99%

Implementation of a Pldro With a Fractional Multiple Frequency of Reference

Chang¹,

Park²

2014

PIER Letters

View full text Add to dashboard Cite

Abstract-A PLDRO (Phase Locked Dielectric Resonator Oscillator) with the output frequency of a fractional multiple of reference is proposed and implemented. The key element in the proposed PLDRO is an image rejection mixer placed between a VCDRO (Voltage Controlled Dielectric Resonator Oscillator) and SPD (Sampling Phase Detector). The image rejection mixer shifts the coupled signal from the VCDRO before the signal feeds the SPD. Therefore, the output frequency of the PLDRO can be realized such that it is not harmonically related with its reference frequency. The frequency divider and multiplier generate the IF frequency for the mixer from the reference frequency. The general PLL (Phase Locked Loop) design parameters such as the damping coefficient and the natural frequency are derived for the proposed topology of the PLDRO. A 7.25 GHz PLDRO with a 100 MHz reference, intended for use as a local oscillator for a ka band Block-up Converter (BUC), is designed and measured. A BJT (Bipolar Junction Transistor) is used as an active component of the VCDRO and a modified two micro-strip line coupled DR model is presented and used for frequency tuning range estimation. The measured phase noise at 10 kHz/100 kHz offset is 101 dBc/Hz and 115 dBc/Hz, respectively. The fabricated PLDRO size is 100 mm by 105 mm by 23 mm including a 100 MHz reference crystal oscillator.

show abstract

On the conception and analysis of a 12-GHz push-push phase-locked DRO

Cited by 34 publications

References 8 publications

Fundamental wave phase-locked dual-band push-push DRO using out-of-phase Wilkinson power combiner

Fundamental wave phase-locked dual-band push-push DRO using out-of-phase Wilkinson power combiner

Design of a 212 GHZ Lo Source Used in the Terahertz Radiometer Front-End

Implementation of a Pldro With a Fractional Multiple Frequency of Reference

Contact Info

Product

Resources

About