On the degradation of p-MOSFETs in analog and RF circuits under inhomogeneous negative bias temperature stress

Schlunder, C.; Brederlow, R.; Ankele, B.; Lill, A.; Goser, K.; Thewes, R.

doi:10.1109/relphy.2003.1197712

Cited by 27 publications

(12 citation statements)

References 5 publications

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“…While increasing the length of PMOS transistors increases the degradation due to NBTI [16][17], increasing the width decreases such degradation [7]. Length is typically set to the minimum possible and only the width is changed to fit timing, power and area constraints.…”

Section: Nbti Physicsmentioning

confidence: 99%

Penelope: The NBTI-Aware Processor

Chu¹,

Ravindran²,

Mahlke³

2007

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)

146

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Section: Nbti Physicsmentioning

confidence: 99%

Penelope: The NBTI-Aware Processor

Chu¹,

Ravindran²,

Mahlke³

2007

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)

146

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“…Besides increasing integration densities, increasing transistor variability [2], [3], process variation [4] and degradation effects [5] add to the design complexity, making it increasingly difficult for manufacturers to fulfill the expectations of their customers with respect to the reliability of the products [6]. For the same reasons, traditional worst-case design becomes less favorable for nano-scale chips, as the design margins that are required to cover the worst cases would use most of the benefits of the next technology node [7].…”

Section: Introductionmentioning

confidence: 99%

Generic Self-Adaptation to Reduce Design Effort for System-on-Chip

Bernauer

Bringmann

Rosenstiel

2009

2009 Third IEEE International Conference on Self-Adaptive and Self-Organizing Systems

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We investigate a generic self-adaptation method to reduce the design effort for System-on-Chip (SoC). Previous self-adaptation solutions at chip-level use circuitries which have been specially designed for the current problem by hand, leading to an elaborate and inflexible design process, requiring specially trained engineers, and making design reuse difficult. On the other hand, a generic self-adaptation method that can be used for various self-adaptation problems promises to reduce the necessary design effort, but may come with reduced performance and other costs.In this paper, we analyze the performance, self-adaptation capabilities and costs of a generic self-adaptation method. The proposed method allows chip-level self-adaptation of a SoC, can tolerate unforeseen events, and can generalize from previous self-adaptation tasks. Furthermore, the method helps to improve the design process by allowing design reuse, providing generic applicability, and offering a uniform design process for various self-adaptation tasks. Simulation results show that the performance of our method lies only 10% below the performance of a perfect, non-adaptive system in the average case, and only 32% in the worst case. In case of unforeseen events, where the performance of a non-adaptive system decreases significantly, the method can keep its performance level by self-adaptation. We also compare other costs involved.

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“…2 V was applied to certify the virtual-floating-body effects of SOI FinFETs, which was similar to a previous study [4]. Detailed fabrication processes have already been reported [2].…”

Section: Introductionmentioning

confidence: 79%

“…As the device is scaled down, the negativebias temperature instability (NBTI) starts to limit the device reliability of digital and analog CMOS circuits [3], [4]. Previous studies indicate an improvement to the negative-biastemperature (NBT) stress with a wide fin width in siliconon-insulator (SOI) and body-tied FinFETs [5], [6].…”

Section: Introductionmentioning

confidence: 99%

A comprehensive modeling of dynamic negative-bias temperature instability in PMOS body-tied FinFETs

Lee

Park

et al. 2006

IEEE Electron Device Lett.

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Abstract-This paper presents a novel approach to estimate the rising and falling behavior of N th-order ON-state current by dynamic negative-bias temperature instability (DNBTI), with a comparison between experimental data and a modified DNBTI model in PMOS body-tied FinFETs for the first time. The modified model was proposed to predict not only N th-order DNBTI behavior but also temperature and stress bias effects. The fin-width dependence was analyzed, and different trends between silicon-on-insulator and body-tied FinFETs were explained with the extracted DNBTI model parameters: stress time, oxide-field strength, and temperature. The proposed model closely matched the measured static lifetime.Index Terms-Body tied, double gate, dynamic negativebias temperature instability (DNBTI), FinFET, floating-body, reliability, silicon-on-insulator (SOI).

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On the degradation of p-MOSFETs in analog and RF circuits under inhomogeneous negative bias temperature stress

Cited by 27 publications

References 5 publications

Penelope: The NBTI-Aware Processor

Penelope: The NBTI-Aware Processor

Generic Self-Adaptation to Reduce Design Effort for System-on-Chip

A comprehensive modeling of dynamic negative-bias temperature instability in PMOS body-tied FinFETs

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