On the Design of a Hardware-Software Architecture for Acceleration of SVM’s Training Phase

Bustio-Martínez, Lázaro; Cumplido, René; Hernández-Palancar, José; Feregrino-Uribe, Claudia

doi:10.1007/978-3-642-15992-3_30

Cited by 4 publications

(5 citation statements)

References 9 publications

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“…Besides SMO, there are also Gilbert's algorithm [24] and Least Squared Support Vector Machine (LS-SVM) [25] for training. Works that are targeted for training either implement the whole system-on-chip or offloaded to a co-processor [2,14,15,16] to accelerate the training process. The task that is targeted for hardware implementation is the kernel as it is a compute-intensive task that benefits from parallelization.…”

Section: Related Workmentioning

confidence: 99%

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A streaming multi-class support vector machine classification architecture for embedded systems

Sirkunan

Tang

Shaikh-Husin

et al. 2019

IJEECS

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<p>Pedestrian detection, face detection, speech recognition and object detection are some of the applications that have benefited from hardware-accelerated SVM. SVM classification computational complexity makes it challenging for designing hardware architecture with real-time performance and low power consumption. On an embedded streaming architecture, test data are stored on external memory and transferred in streams to the FPGA device. The hardware<br />implementation for SVM classification needs to be fast enough to keep up with the data transfer speed. Prior implementation throttles data input to avoid overwhelming the computational unit. This results in a bottleneck in overall streaming architecture as maximum throughput could not be obtained. In this work, we propose a streaming architecture multi-class SVM classification for embedded system that is fully pipelined and able to process data continuously with out any need to throttle data stream input. The proposed design is targeted for embedded platform where test data is transferred in streams from an external memory. The architecture was implemented on Altera Cyclone IV platform. Performance analysis on our proposed architecture is done with regards to the number of features and support vectors. For validation, the results obtained is compared with LibSVM. The proposed architecture is able to produce output rate identical to test data input rate.</p>

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Section: Related Workmentioning

confidence: 99%

“…These designs cannot be easily reused for other applications as they are optimized for specific applications [8]. Works that targeted on acceleration of SVM with a co-processor unit [2,14,15,16] tend to focus on the kernel due to its compute-intensive task and also its innate nature to be parallelized.…”

Section: Introductionmentioning

confidence: 99%

A streaming multi-class support vector machine classification architecture for embedded systems

Sirkunan

Tang

Shaikh-Husin

et al. 2019

IJEECS

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“…Martinez, et al [17] designed a heterogeneous architecture to accelerate SVM training phase. To reduce the dot-product computation time, these operations were affected by the hardware coprocessor of Xtreme DSP Virtex-IV whereas the hierarchy of SMO algorithm was implemented in GPP.…”

Section: A Fpga: Hardware Acceleratormentioning

confidence: 99%

Implementation of the RN Method on FPGA using Xilinx System Generator for Nonlinear System Regression

Sayehi¹,

Touali²,

Saidani³

et al. 2017

ijacsa

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Abstract-In this paper, we propose a new approach aiming to ameliorate the performances of the regularization networks (RN) method and speed up its computation time. A considerable rapidity in totaling calculation time and high performance were accomplished through conveying difficult calculation charges to FPGA. Using Xilinx System Generator, a successful HW/SW CoDesign was constructed to accelerate the Gramian matrix computation. Experimental results involving two real data sets of Wiener-Hammerstein benchmark with process noise prove the efficiency of the approach. The implementation results demonstrate the efficiency of the heterogeneous architecture, presenting a speed-up factor of 40-50 orders of time, comparing to the CPU simulation.

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“…Besides SMO, there are also Gilbert's algorithm [20] and LS-SVM [21] for training. Works that are targeted for training either implements the whole system onchip or offloading to a co-processor [1], [10]- [12] to accelerate the training process. The task that is targeted for hardware implementation is the kernel as it is compute-intensive task that benefit from parallelization.…”

Section: Kernel Functionmentioning

confidence: 99%

“…Works that targeted on accelerating SVM with a coprocessor unit [1], [10]- [12] tend to focus on the kernel due to its compute-intensive task and also its innate nature to be parallelize. Prior work by Kane et al [13] implemented a generic SVM classification architecture that was tested with a wide variety of datasets.…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable Logic Embedded Architecture of Support Vector Machine Linear Kernel

Sirkunan¹,

Shaikh-Husin²,

Andromeda³

et al. 2017

EECSI

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Support Vector Machine (SVM) is a linear binary classifier that requires a kernel function to handle non-linear problems. Most previous SVM implementations for embedded systems in literature were built targeting a certain application; where analyses were done through comparison with software implementations only. The impact of different application datasets towards SVM hardware performance were not analyzed. In this work, we propose a parameterizable linear kernel architecture that is fully pipelined. It is prototyped and analyzed on Altera Cyclone IV platform and results are verified with equivalent software model. Further analysis is done on determining the effect of the number of features and support vectors on the performance of the hardware architecture. From our proposed linear kernel implementation, the number of features determine the maximum operating frequency and amount of logic resource utilization, whereas the number of support vectors determines the amount of on-chip memory usage and also the throughput of the system.

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On the Design of a Hardware-Software Architecture for Acceleration of SVM’s Training Phase

Cited by 4 publications

References 9 publications

A streaming multi-class support vector machine classification architecture for embedded systems

A streaming multi-class support vector machine classification architecture for embedded systems

Implementation of the RN Method on FPGA using Xilinx System Generator for Nonlinear System Regression

Reconfigurable Logic Embedded Architecture of Support Vector Machine Linear Kernel

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