On the design of new low-power CMOS standard ternary logic gates

Doostaregan, Akbar; Moaiyeri, Mohammad Hossein; Navi, Keivan; Hashemipour, Omid

doi:10.1109/cads.2010.5623544

Cited by 15 publications

(4 citation statements)

References 15 publications

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“…2 a , which is based on PTI and NTI gates. The outputs of the PTI and NTI gates are connected together by means of two capacitors that make a weighting sum of their inputs [35]. The voltage of the connection node of the capacitors is calculated as follows

V_{STI} = \frac{C_{N} V_{N} + C_{P} V_{P}}{C_{N} + C_{P}}

…”

Section: Proposed Low‐power Cntfet‐based Mvl Circuitsmentioning

confidence: 99%

A universal method for designing low‐power carbon nanotube FET‐based multiple‐valued logic circuits

Moaiyeri

Mirzaee

Doostaregan

et al. 2013

IET Computers & Digital Techniques

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105

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This study presents new low-power multiple-valued logic (MVL) circuits for nanoelectronics. These carbon nanotube field effect transistor (FET) (CNTFET)-based MVL circuits are designed based on the unique characteristics of the CNTFET device such as the capability of setting the desired threshold voltages by adopting correct diameters for the nanotubes as well as the same carrier mobility for the P-and N-type devices. These characteristics make CNTFETs very suitable for designing high-performance multiple-Vth circuits. The proposed MVL circuits are designed based on the conventional CMOS architecture and by utilising inherently binary gates. Moreover, each of the proposed CNTFET-based ternary circuits includes all the possible types of ternary logic, that is, negative, positive and standard, in one structure. The method proposed in this study is a universal technique for designing MVL logic circuits with any arbitrary number of logic levels, without static power dissipation. The results of the simulations, conducted using Synopsys HSPICE with 32 nm-CNTFET technology, demonstrate improvements in terms of power consumption, energy efficiency, robustness and specifically static power dissipation with respect to the other state-of-the-art ternary and quaternary circuits.

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V_{STI} = \frac{C_{N} V_{N} + C_{P} V_{P}}{C_{N} + C_{P}}

…”

Section: Proposed Low‐power Cntfet‐based Mvl Circuitsmentioning

confidence: 99%

A universal method for designing low‐power carbon nanotube FET‐based multiple‐valued logic circuits

Moaiyeri

Mirzaee

Doostaregan

et al. 2013

IET Computers & Digital Techniques

Self Cite

105

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“…Figures 7, 8, 9, 10, 11and 12 shows simulation results of ternary INVERTER, TNAND, TNOR, TAND, TOR and TBUFFER. Table 7 shows comparison of Transistor count with existing designs in [5], [6], [7].…”

Section: Results and Observationsmentioning

confidence: 99%

Implementation of ternary logic gates using FGMOS

Gopal

Narkhede

Sasikala

2015

2015 International Conference on Smart Technologies and Management for Computing, Communication, Controls, Energy and Materials

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Inthis paper we present the ternary logic gates implementation using FGMOS (Floating gate MOSFET) also calledMIFG MOSFET (Multi input floating gate MOSFET). Implementationusing ternary logic have advantage than binary logic implementation in terms of more information capability, reduced interconnections and reduction in chip area. MIFG MOSFETs design reduces transistor count as a result area of chip will reduce. Ternary logic gates using MIFG MOSFETs reduces transistor count compared with CMOS design and CNTFET based designs. Keywords-FGMOS, MIFG MOSFET, Ternary logic, Binary logic, CMOS and CNTFET.

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“…To get the complexity and power consumption of the ternary basic gates designed based on MOSFET further reduced, reference [24] proposed a design method that only a single power supply exists, which not only reduced the overall power consumption of the circuit but also improved the transition time. Reference [25] mentioned a novel STI design, the main idea of which bases on weighting method. The output values of the PTI and NTI gates are added through two capacitors to improve the circuit performance, and there are no additional resistors in the circuit.…”

Section: Design Of Ternary Logic Gates Based On Mosfetsmentioning

confidence: 99%

A review on the design of ternary logic circuits*

Wang

Dong

2021

Chinese Phys. B

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A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity, power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.

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On the design of new low-power CMOS standard ternary logic gates

Cited by 15 publications

References 15 publications

A universal method for designing low‐power carbon nanotube FET‐based multiple‐valued logic circuits

A universal method for designing low‐power carbon nanotube FET‐based multiple‐valued logic circuits

Implementation of ternary logic gates using FGMOS

A review on the design of ternary logic circuits*

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