On the design of prunable interleavers for turbo codes

Eroz, Mustafa; Hammons, A.R.

doi:10.1109/vetec.1999.780687

Cited by 34 publications

(15 citation statements)

References 3 publications

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“…Although the complicated operations and parameters used in interleaving are quite different, W-CDMA and cdma2000 share the general concept of prunable block interleavers presented in [14]. They can implement interleavers of arbitrary size by first building the mother interleaver of a predefined size and then pruning unnecessary indexes.…”

Section: A Prunable Interleaversmentioning

confidence: 99%

SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards

Myoung-Cheol

Park

2007

IEEE Trans. VLSI Syst.

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Abstract-A programmable turbo decoder is designed to support multiple third-generation wireless communication standards. We propose a hybrid architecture of hardware and software, which has small size, low power, and high performance like hardware implementations, as well as the flexibility and programmability of software. It mainly consists of a configurable hardware soft-inputsoft-output (SISO) decoder and a 16-b single-instruction multipledata processor, which is equipped with five processing elements and special instructions customized for interleaving in order to provide interleaved data at the speed of the hardware SISO. A fast and flexible software implementation of the block interleaving algorithm is also proposed. The interleaver generation is split into two parts, preprocessing and on-the-fly generation, to reduce the timing overhead of changing the interleaver structure. We present detailed descriptions of the interleaving implementation applied to the W-CDMA and cdma2000 standard turbo codes. The decoder occupies 8.90 mm 2 in a 0.25-m CMOS with five metal layers and exhibits the maximum decoding rate of 5.48 Mb/s. Index Terms-cdma2000, parallel algorithm, turbo code, turbo interleaver, W-CDMA.

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Section: A Prunable Interleaversmentioning

confidence: 99%

SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards

Myoung-Cheol

Park

2007

IEEE Trans. VLSI Syst.

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“…On the contrary, pruning is a viable technique if we are free to design the permutation so that it is robust to this operation: This approach was followed in References [49][50][51][52]. All techniques, with the exception of Reference [50], are based on the expansion of a small interleaver with an incremental algorithm.…”

Section: Block Size Versatilitymentioning

confidence: 99%

“…All techniques, with the exception of Reference [50], are based on the expansion of a small interleaver with an incremental algorithm. In Reference [53] an approach similar to Reference [51] was used to build a family of prunable S-random interleavers.…”

Section: Block Size Versatilitymentioning

confidence: 99%

Design issues in the implementation of versatile, high‐speed iterative decoders

Benedetto

Dinoi

Montorsi

et al. 2007

Trans Emerging Tel Tech

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SUMMARYThe ever increasing demand for high data rate communication, and the use of radio resource management techniques requiring frame-by-frame adaptive coding/modulation to match user demands and channel conditions, pose a number of crucial problems to the design of versatile, high-speed iterative decoders, for both turbo-like and low-density parity-check codes. Among them, we mention:The modification of the Soft-Input Soft-Output (SISO) algorithm in a way that permits its implementation using several parallel processors working independently on segments of the received frame. The collisions in the process of reading/writing into/from the memory by the parallel processors. The design of prunable interleavers covering a wide range of information and/or code words lengths while keeping good spreading properties. The design of codes yielding a wide range of code rates with good performance for the range of probability of error of interest.The paper will touch all the previous points, offering state-of-the art solutions and examples showing their performance.

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“…Pruning is a technique used to support more flexible block lengths [4][5][6]. Communication standards [7][8][9] typically vary the block length depending on the input data rate requirements and channel conditions.…”

Section: Introductionmentioning

confidence: 99%

On the contention-free and spread characteristics of serially-pruned interleavers

Mansour

2013

2013 IEEE International Conference on Acoustics, Speech and Signal Processing

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Serial pruning of turbo interleavers have been proposed in the literature as a simple scheme to provide more flexible codeword lengths. In this paper, we prove two important attributes about serially pruned interleavers. First, we show that serially pruned interleavers inherit the content-free property of their mother interleaver, and hence they remain parallelizable. An example serially-pruned QPP LTE interleaver is parallelized. Second, the minimum spread factor of a serially-pruned interleaver closely matches the spread factor of its mother interleaver for small pruning gaps with minimal impact on BER performance, and degrades gracefully with the pruning length. Simulation results of practical pruned LTE turbo interleavers demonstrate the graceful degradation of spread characteristics and BER performance of serially pruned interleavers.

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On the design of prunable interleavers for turbo codes

Cited by 34 publications

References 3 publications

SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards

SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards

Design issues in the implementation of versatile, high‐speed iterative decoders

On the contention-free and spread characteristics of serially-pruned interleavers

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