On the design of scalable and reusable accelerators for big data applications

Abstract

Accelerators are becoming key elements of computing platforms for both data centers and mobile devices as they deliver energyefficient high performance for key computational kernels. However, the design and integration of such components is complex, especially for Big Data applications where they have very large workloads to elaborate. Properly customizing the accelerators' private local memories (PLMs) is of critical importance. To analyze this problem we design an accelerator for Collaborative Filtering by applying a system-level design methodology that allows us to synthesize many alternative micro-architectures as we vary the PLM sizes. We then evaluate the resulting accelerators in terms of resource requirements for both embedded architectures and data centers as we vary the size and density of the workloads.

Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification

“…Restricted Boltzmann Machine (RBM) is a stochastic neural network commonly used in recommendation systems. We model the RBM accelerator from the Columbia System Level Design Group [55]. It is implemented in SystemC and synthesized to Verilog.…”

“…We check ILA vs. FSM equivalence for two accelerators and a general purpose processor. All FSM models are provided independently by other groups, and not synthesized from ILAs: RBM-SystemC model by the Carloni-Columbia group [55]; Gaussian-Blur-Halide/C++ model by the Horowitz-Stanford group [56]; AES-C/RTL implementation from OpenCores.org [38]; RISC-V implementation from Berkeley's Rocket-chip generator [8]. Our previous work [62,64] has discussed the verification of the 8051 micro-controller and SHA accelerator, where 8 bugs were found in the RTL model in 8051.…”