On The Development of a Reliable Gate Stack for Future Technology Nodes Based on III-V Materials

Abstract

In this work, we discuss how the insertion of a LaSiO x layer in between an in-house IL passivation layer and the high-k has moved the III-V gate stack into the target window for future technology nodes. The insertion of this LaSiO x layer in the gate stack has reduced the D it and N bt below the target level of 5x10 11 /eV.cm 2 and 3x10 10 /cm 2 (target at 10 years operation: ΔV fb <30mV at 125°C) respectively. From physical analysis, it was found that LaSiO x can stabilize the interaction of the IL layer with the InGaAs substrate. An implant free In 0.53 Ga 0.47 As n-MOSFET was fabricated with this gate stack and for the first time, a III-V gate stack meets the reliability target for advanced technology nodes with a max operating V ov of 0.6 V. In addition, an excellent electron mobility (µ eff , peak =3531 cm 2 /V-s), low SS lin =71 mV/dec and an EOT of 1.15 nm were obtained. We also report the scaling potential of this stack to 1 nm EOT without any loss in performance, reliability and further reduction of the sub-threshold swing (SS lin =68 mV/dec).

Characterization of High-Performance InGaAs QW-MOSFETs With Reliable Bi-Layer HfOxNy Gate Stack

“…5, remarkable subthresholdslope (SS) improvement was observed by employing the IPA-based HfO x N y IL. The extracted SS value at the gate length of 20 µm was 77, 76, and 72 mV/dec at V D = 0.5 V devices [10]. It suggests that an extraordinary interface quality can be achieved with the IL of this work.…”

“…The maximum operating overdrive voltage (V OV ) that ensures 10 year reliability was estimated to be 0.49 V and 0.32 V for sample B and C, respectively. It is worth mentioning that the maximum V OV targets for the accumulation mode III-V MOSFETs of V DD = 0.5 V and 0.75 V are 0.33 V and 0.5 V, respectively [10]. The proposed bi-layer gate stack achieved these values successfully even on low CET.…”

“…In addition, the positive bias temperature instability (PBTI) characteristics were measured for sample B and C in order to investigate the advantage of using bi-layer gate stack scheme further. The PBTI stress measurements were performed using the measure-stress-measure technique under various positive gate stress voltages [10], [17], [18]. The amount of threshold voltage shift V th under high gate stress bias represents the electron trapping rate in defects located at both the interfacial layer and the bulk high-k dielectric.…”

“…Direct deposition of HfO 2 on InGaAs substrate has been difficult to use due to large density electron traps and the approach to employ bi-layer high-k schemes with the improved interface layer (IL) has become the common strategy to address the goal of thin effectiveoxide-thickness (EOT) and good interface quality simultaneously [6], [8]- [10]. Among several IL candidates, Al 2 O 3 has been the dominant high-k IL in III-V MOS research due to its strong advantage of 'self-cleaning effect' [6], [7], [12].…”

“…Recently, it was reported that the polycrystalline AlN is effective to passivate the III-V surface dangling bonds in conjunction with a substantial improvement in the gate stack reliability [18]. Also, the most advanced results were recently reported by using the combination of unknown ALD IL material which was developed with ASM system referred to as ASM-IL (κ-value ∼6) and LaSiO x on the InGaAs substrate [10]. It was suggested that the developed IL might form a more favorable defect band distribution and a further reduction on the oxide defects.…”