On the Efficacy of Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption

Zhang, Yucong; Holst, Stefan; Wen, Xiaoqing; Miyase, Kohei; Kajihara, Seiji; Qian, Jun

doi:10.1587/transinf.2020edp7042

Cited by 2 publications

(4 citation statements)

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“…(II) Another approach is changing scan chain clocking. Numerous implementations with flexible control of clocks to drive scan chains [8], [10], [12], [15], [23], such as staggered clocks based on different duty cycles or phases, scan segmentation, and scan chain disable, are available. The common feature of these techniques is that only a subset of scan chains is shifted at a time, i.e.…”

Section: Reduction Of Ir-drop In Scan Shiftingmentioning

confidence: 99%

“…Furthermore, an algorithm is proposed to assign scan flip-flops to shift clock domains to reduce peak shift power [11]. The optimal static grouping of scan chains for partial shifting has been tackled for reducing SSA hot-spots around scan flip-flops [8] and clock buffers [25].…”

Section: Reduction Of Ir-drop In Scan Shiftingmentioning

confidence: 99%

“…1) Overheating due to the accumulative impact of shift power may damage a circuit or increase test cost. 2) Shift failure due to excessive shift power induced IR-drop along clock paths or in the power supply of scan flip-flops will cause wrong data to be shifted [6]- [8]. 3) Capture failure due to excessive capture power induced IR-drop along data paths will cause a false response to be captured.…”

Section: Introductionmentioning

confidence: 99%

“…Several methods have been proposed to reduce power or IR-drop in shift mode based on partial-shift [8], [10]- [12]. The principle of reducing excessive SSA-induced IRdrop is to add additional cycles so that scan chains can not be shifted simultaneously.…”

Section: Introductionmentioning

confidence: 99%

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GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting

SHI,

HOLST,

WEN

2023

IEICE Trans. Inf. & Syst.

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High power dissipation during scan test often causes undue yield loss, especially for low-power circuits. One major reason is that the resulting IR-drop in shift mode may corrupt test data. A common approach to solving this problem is partial-shift, in which multiple scan chains are formed and only one group of scan chains is shifted at a time. However, existing partial-shift based methods suffer from two major problems:(1) their IR-drop estimation is not accurate enough or computationally too expensive to be done for each shift cycle; (2) partial-shift is hence applied to all shift cycles, resulting in long test time. This paper addresses these two problems with a novel IR-drop-aware scan shift method, featuring: (1) Cycle-based IR-Drop Estimation (CIDE) supported by a GPU-accelerated dynamic power simulator to quickly find potential shift cycles with excessive peak IR-drop; (2) a scan shift scheduling method that generates a scan chain grouping targeted for each considered shift cycle to reduce the impact on test time. Experiments on ITC'99 benchmark circuits show that: (1) the CIDE is computationally feasible; (2) the proposed scan shift schedule can achieve a global peak IR-drop reduction of up to 47%. Its scheduling efficiency is 58.4% higher than that of an existing typical method on average, which means our method has less test time.

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