On-the-fly programmable hardware for networks

Hadzic, Ilija; Smith, Jonathan M.; Marcus, W.S.

doi:10.1109/glocom.1998.776848

Cited by 32 publications

(14 citation statements)

References 12 publications

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“…The idea is nevertheless present, as has been shown in the work of Hadzic et al at the University of Pennsylvania [7] and Decasper et al at Washington University at St. Louis [4] and recently also in the work of Dr. Zitterbart´s group at the University of Braunschweig [8]. The P4 architecture, developed under the Protocol Boosters project [6] at UPenn consists of a pipeline of FPGAs interconnected by a switching array and controlled by a special Controller Unit.…”

Section: Previous Workmentioning

confidence: 77%

The Octopus Network Model: Opening Up the Internet to Active and Programmable Network Implementations

Macian

2001

Active Networks

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Abstract. The inclusion of innovative services in commercial networks is a burdensome task which frequently encounters resistance from Network Operators. Opening up the network is a prerequisite for the Active & Programmable Network paradigm to succeed. In this paper we present a novel network model which addresses three critical points to achieve that goal: network security and safety, service management and high performance. We show that excessive virtualization of network resources penalizes performance and we introduce programmable hardware at the core of our model. We also introduce a two-tier security checking architecture which frees network nodes from the most heavyweight tasks, improving performance. Our single point of service admission permits strict security control. Lastly, the separation between service introduction and service management increases network flexibility and permits the smooth integration of other network architectures in our framework. We also present the Octopus Open Gateway architecture, which shall support our network model.

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Section: Previous Workmentioning

confidence: 77%

The Octopus Network Model: Opening Up the Internet to Active and Programmable Network Implementations

Macian

2001

Active Networks

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“…In [5], a reconfigurable system called Programmable Protocol Processing Pipeline (P4) has been introduced. In this case, a set of FPGAs is used in a pipeline way in order to accelerate the packets processing.…”

Section: Related Workmentioning

confidence: 99%

A reconfigurable platform for multi-service edge routers

Kachris

Vassiliadis

2007

Proceedings of the 20th Annual Conference on Integrated Circuits and Systems Design

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A main feature of current FPGAs is that they can be dynamically reconfigured to meet the network traffic requirements. In this paper we present a case study for a multi-service edge router in which the number of processors and co-processors is dynamically reconfigured to meet the network traffic workload. The system targets the Xilinx Virtex4 FPGA platform and uses the MicroBlaze soft processors for header processing and hardware acceleration units for payload processing. Furthermore, two schemes are compared for the reconfiguration of the system. The first one has fast response time but is prone to network burst traffic while the second one has slower response time but is more robust to burst traffic. The performance evaluation shows that the reconfigurable platform can achieve up to 1.5x speedup compared to a static system.

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“…Significant work has already been done in reconfigurable network hardware: specifically, the P4 developed at the University of Pennsylvania [7]. By dynamically switching FPGAs in and out of the datapath, flows can be routed through chains of applications while other applications are loaded into idle FPGAs.…”

Section: Background and Related Workmentioning

confidence: 99%

Dynamic hardware plugins: exploiting reconfigurable hardware for high-performance programmable routers

2002

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This paper presents the dynamic hardware plugins (DHP) architecture for implementing multiple networking applications in hardware at programmable routers. By enabling multiple applications to be dynamically loaded into a single hardware device, the DHP architecture provides a scalable mechanism for implementing high-performance programmable routers. The DHP architecture is presented within the context of a programmable router architecture which processes flows in both software and hardware. Implementation options are described as well as the prototype testbed at Washington University in Saint Louis which utilizes the partial reconfiguration capability of modern field programmable gate arrays. Ó 2002 Published by Elsevier Science B.V.

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On-the-fly programmable hardware for networks

Cited by 32 publications

References 12 publications

The Octopus Network Model: Opening Up the Internet to Active and Programmable Network Implementations

The Octopus Network Model: Opening Up the Internet to Active and Programmable Network Implementations

A reconfigurable platform for multi-service edge routers

Dynamic hardware plugins: exploiting reconfigurable hardware for high-performance programmable routers

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