Abstract. The integrated circuit (IC) industry is in the midst of an explosive expansion of new materials, processes and tools utilized in the fabrication of ICs and, accordingly, there are a host of associated new challenges and opportunities. These include, for example, the implementation of 300mm diameter wafers, the drive to equivalent oxide thickness in the sub-1.0 nanometer regime for high-performance logic devices via high-k gate-dielectric materials and metal gate electrodes, strained silicon methodologies, the expanded utilization of silicon-on-insulator (SOI) materials, copper metallization, low-k inter-level dielectrics and a plethora of alternative transistor configurations in non-classical CMOS device structures. We will discuss the implications of these advanced materials and device configurations on the International Technology Roadmap for Semiconductors (ITRS).