On the in-field test of Branch Prediction Units using the correlated predictor mechanism

Gaudesi, Marco; Saleem, Sheena; Sanchez, E.; Reorda, M. Sonza; Tanowe, E.

doi:10.1109/ddecs.2014.6868811

Cited by 1 publication

(1 citation statement)

References 11 publications

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“…In order to reduce the branch misprediction penalty raised due to branch correlating, two levels of history should be used to guess the branch direction. The first level holds the patterns of former branches, while the second level catches the branch directions associated with the last occurrence of a particular pattern in the first level [14,15]. Here is a summarized illustration of how the feature of two history levels is employed in designing some types of branch prediction schemes.…”

Section: Theoretical Features Of Correlated Predictionmentioning

confidence: 99%

FPGA configuration of an alloyed correlated branch predictor used with RISC processor for educational purposes

Mahmood

2021

IJECE

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Instructions pipelining is one of the most outstanding techniques used in improving processor speed; nonetheless, these pipelined stages are constantly facing stalls that caused by nested conditional branches. During the execution of nested conditional branches, the behavior of the running branch depends on the history information of the previous ones; therefore, these branches have the greatest effect in reducing the prediction accuracy of a branch predictor among conditional branches. The purpose of this research is to reduce the stall cycles caused by correlated branches misprediction by introducing a hardware model of a branch predictor that combines both local and global prediction techniques. This predictor integrates the prediction characteristics of the alloyed predictor with those of the correlated predictor. the predictor design which implemented in VHDL (Very high-speed IC hardware description language) was inserted in previously designed MIPS (microprocessor without interlocked pipelined stages) processor and its prediction accuracy was confirmed by executing a program using the selection sort algorithm to sort 100 input numbers of different combinations ascendingly.

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Section: Theoretical Features Of Correlated Predictionmentioning

confidence: 99%

FPGA configuration of an alloyed correlated branch predictor used with RISC processor for educational purposes

Mahmood

2021

IJECE

View full text Add to dashboard Cite

show abstract

On the in-field test of Branch Prediction Units using the correlated predictor mechanism

Cited by 1 publication

References 11 publications

FPGA configuration of an alloyed correlated branch predictor used with RISC processor for educational purposes

FPGA configuration of an alloyed correlated branch predictor used with RISC processor for educational purposes

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