On the maturity of parallel applications for asymmetric multi-core processors

Chronaki, Kallia; Moretó, Miquel; Casas, Marc; Rico, Alejandro; Badía, Rosa M.; Ayguadé, Eduard; Valero, Mateo

doi:10.1016/j.jpdc.2019.01.007

Cited by 11 publications

(24 citation statements)

References 33 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For the same task, the energy efficiency of little cores is much better than that of big cores [ 36 ]. To further improve the execution efficiency of these processors, many studies about task mapping and thread switching were also conducted [ 37 , 38 , 39 ].…”

Section: Related Workmentioning

confidence: 99%

An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture

Qiao

Gao

et al. 2021

Micromachines

View full text Add to dashboard Cite

Embedded processors are widely used in various systems working on different tasks with different workloads. A more complex micro-architecture leads to better peak performance and worse power consumption. Shutting down the units designed for performance enhancement could improve energy efficiency in low-workload scenarios. In this paper, we evaluated the energy distribution in various embedded processors. According to the analysis, pipeline registers and the dynamic branch predictor, which are employed for better peak performance, have great impacts on energy efficiency. Thus, we proposed an ultra-low-power processor with variable micro-architecture. The processor is based on a 4-stage pipeline core with a Gshare branch predictor, and all units work in high-performance mode. In normal mode, the Gshare predictor is shut down and Always-Not-Taken prediction is used. In low-power mode, some of the pipeline registers are bypassed to avoid unnecessary energy dissipation and improve executing efficiency. A mode register (MR) is designed to indicate current working mode. Switching between different modes is controlled by the software. The proposed core is implemented in 40 nm technology and simulated with the traces of 17 benchmarks in Embench. The average amounts of power consumed by the respective modes are 41.7 W, 59.7 W and 71.1 W. The results show that normal mode (N-mode) and low-power mode (L-mode) consume 16.08% and 41.37% less power than high-performance mode (H-mode) on average. In best case scenarios, they could save 25.36% and 49.30% more power than H-mode. Considering the execution efficiency evaluated by instructions per cycle (IPC), the proposed processor consumes 7.78% or 51.57% less energy for each instruction than the baseline core. The area of the proposed processor is only 7.19% larger than the baseline core, and only 3.08% more power is consumed in H-mode.

show abstract

Section: Related Workmentioning

confidence: 99%

An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture

Qiao

Gao

et al. 2021

Micromachines

View full text Add to dashboard Cite

show abstract

“…Chronaki, Casas, Rico, Valero, Moreto, Badia and Ayguadé perform in On the Maturity of Parallel Applications for Asymmetric Multi-Core Processors [2] an extensive evaluation of the portability of HPC applications for asymmetric multicore architectures, with a focus on runtime level scheduler vs OS scheduling solutions. The experimental results in the paper show that scheduling is more effective when it takes place in the runtime supporting the parallel execution model as it improves the baseline by 23%, while the heterogeneous-aware OS scheduling solution improves the baseline by 10%.…”

Section: Special Issue Contentsmentioning

confidence: 99%

Trends on heterogeneous and innovative hardware and software systems

Melo

Carretero

Stenström

et al. 2019

Journal of Parallel and Distributed Computing

View full text Add to dashboard Cite

“…Despite the remarkable benefits of AMPs, 6 effectively scheduling diverse programs/tasks on heterogeneous cores poses a significant challenge to the various system software layers. 2,[7][8][9][10] When a single multithreaded application runs alone on an AMP system, smart user-level scheduling within the runtime system is the key to making the most out of its heterogeneous cores. 7,11 However, in multi-application scenarios, and especially under the presence of legacy programs, the OS scheduler plays an essential role in transparently delivering the benefits of AMPs to the end user.…”

mentioning

confidence: 99%

“…2,[7][8][9][10] When a single multithreaded application runs alone on an AMP system, smart user-level scheduling within the runtime system is the key to making the most out of its heterogeneous cores. 7,11 However, in multi-application scenarios, and especially under the presence of legacy programs, the OS scheduler plays an essential role in transparently delivering the benefits of AMPs to the end user. 2,9,12,13 In our work, we focus on designing and implementing effective OS and runtime-level schedulers to deal with single-and multi-application scenarios, by leveraging smart interaction between system software layers when possible.…”

mentioning

confidence: 99%

“…Many of these applications are broadly used in scientific and engineering domains, and constitute the dominant application type in many parallel benchmark suites extensively used for performance evaluation on symmetric and asymmetric multicore systems. 7,11,[14][15][16][17][18][19] Some of our insights on effective OS-runtime interaction techniques could be leveraged for other types of programs, such as the increasingly popular task-based parallel applications, where runtime scheduling has also drawn special attention. 10,[20][21][22] Previous research has demonstrated that the runtime system and the OS scheduler can perform optimizations on AMPs by leveraging hardware features that are directly controlled by the OS kernel and exposed to user space, such as performance monitoring counters (PMCs) 4,12,23 or dynamic voltage and frequency scaling (DVFS).…”

mentioning

confidence: 99%

See 1 more Smart Citation

Flexible system software scheduling for asymmetric multicore systems with PMCSched: A case for Intel Alder Lake

Bilbao

Sáez

Prieto-Matías

2023

Concurrency and Computation

View full text Add to dashboard Cite

SummaryAsymmetric multicore processors (AMPs) couple high‐performance big cores and power‐efficient small ones, all exposing a shared instruction set architecture to software, but with different microarchitectural features. The energy efficiency benefits of AMPs, together with the general‐purpose nature of the various cores, have led hardware manufacturers to build commercial AMP‐based products, first for the mobile and embedded domains, and more recently, for the desktop market segment, as with the Intel Alder Lake processor family. This trend indicates that AMPs may become a solid and more energy efficient replacement for symmetric multicores in a wide range of application domains. Previous research has demonstrated that the system software can substantially improve scheduling—critical to get the most out of heterogeneous cores—by leveraging hardware facilities that are directly managed by the OS, such as performance monitoring counters, or the recently introduced Intel Thread Director technology. Unfortunately, the OS‐level support enabling access to these hardware facilities may often take a long time to be adopted in operating systems, or may come in forms that make its utilization challenging from specific levels of the system software stack, especially in production systems. To fill this gap, we propose PMCSched, an open‐source framework enabling rapid development and evaluation of custom scheduling‐related support in the Linux kernel. PMCSched greatly simplifies the design and implementation of a wide range of scheduling policies for multicore systems that operate at different system software layers without requiring to patch the kernel. To demonstrate the potential of our framework, we conduct a set of experimental case studies on asymmetry‐aware scheduling for Intel Alder Lake processors.

show abstract

On the maturity of parallel applications for asymmetric multi-core processors

Cited by 11 publications

References 33 publications

An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture

An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture

Trends on heterogeneous and innovative hardware and software systems

Flexible system software scheduling for asymmetric multicore systems with PMCSched: A case for Intel Alder Lake

Contact Info

Product

Resources

About