On the Meaning of SysML Activity Diagrams

Jarraya, Yosr; Debbabi, Mourad

doi:10.1109/ecbs.2009.25

Cited by 16 publications

(4 citation statements)

References 19 publications

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“…In the paper [14], authors propose a formal syntax and semantics for SysML activity diagrams. The main contribution consists in defining a formal language, namely Activity Calculus (AC), with a formal operational semantics.…”

Section: Related Workmentioning

confidence: 99%

Formal verification of components assembly based on SysML and interface automata

Chouali

Hammad

2011

Innovations Syst Softw Eng

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We propose an approach which combines component SysML models and interface automata in order to assemble components and to verify formally their interoperability. So we propose to verify formally the assembly of components specified with the expressive and semi-formal modeling language, SysML. We specify component-based system architecture with SysML Block Definition Diagram, and the composition links between components with Internal Block Diagrams. Component's protocols are specified with sequence diagrams, they are necessary to exploit interface automata formalism. Interface automata is a common Input Output (I/O) automata-based formalism intended to specify the signature and the protocol level of the component interfaces. We propose formal specifications for SysML semi-formal models in order to exploit interface automata approach. We also improve the interface automata approach by considering system architecture, specified with SysML, in the verification of components composition.Keywords SysML · Components composition · Interface automata ProblematicIncreasingly, the demand in industry field for efficient systems those are usually embedded and hybrid is growing exponentially. The design, the development, and the guarantee of high reliability and good performance of such systems have become a challenge. The complexity of embedded systems, the heterogeneity of their components, and the criticality of their requirements lead to develop a design process based on the simulation and verification of these systems before their deployment in vehicles, aircraft, …. The success or failure of the design are played primarily during the modeling phase of the specification. At this stage, the challenge is to define objectives understood by all, exhaustively covering the vision of the whole project, and to use representations to communicate between the involved actors as users, analysts and experts in the field, for this the graphical models are the most adapted.The SysML language is a UML profile, that is a language for documenting and graphically specify all aspects of a system consisting of hardware and/or software blocks. SysML enjoys unprecedented popularity both in industry and academia. It is in the form of graphical models, used to harmonize the different actors contributing to the achievement of a system, and to ensure consistency and quality of design. It is a language well suited to model embedded systems, in addition to the hierarchical model of hardware blocks and software, it allows to model the mathematical equations graphically by defining the physical behavior of these systems. This language was adopted recently by the Object Management Group (OMG) [1] as a standard in systems engineering. Nevertheless, despite the various advantages of SysML, it remains a semi-formal language without the possibility to directly simulate or verify the described models formally.In this paper, we focus on the component-based systems, and propose to verify formally the assembly of their components which are specified in the fir...

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Section: Related Workmentioning

confidence: 99%

Formal verification of components assembly based on SysML and interface automata

Chouali

Hammad

2011

Innovations Syst Softw Eng

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“…[10], [11], [18]. Most of the research work done on UML is applicable to SysML, as SysML is the extension of UML.…”

Section: Related Workmentioning

confidence: 99%

An approach: SysML-based automated requirements verification

Morkevičius

Jankevičius²

2015

2015 IEEE International Symposium on Systems Engineering (ISSE)

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Systems Modeling Language (SysML) is used to capture systems design as descriptive and analytical system models, which relate text-based requirements to the system design model and provide an infrastructure to support analysis and verification. However, SysML is not a methodology, nor a method. This opens-up discussions of how to utilize SysML provided infrastructure to successfully achieve analysis and verification objectives in the context of a particular engineering problem. In this paper a new approach of how model of the system, expressed with sufficient precision in SysML, can be used to support early requirements validation and design verification, particularly when coupled with standard-based execution and simulation environment, is introduced.

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“…En [10] se presenta un lenguaje algebraico llamado cálculo de actividades para especificar formalmente los diagramas de actividades de SysML. Mediante este lenguaje se puede verificar si los diagramas de actividades cumplen con todas las reglas especificadas en el documento oficial de la OMG [16].…”

Section: F Valles-barajasunclassified

“…En la versión 2.0 de UML los diagramas de actividades dejaron de estar relacionados con los diagramas de estados y por lo tanto todos las definiciones formales que fueron hechas de la versión 1.x de UML ya no aplican. Lo interesente de [10] es que formaliza los diagramas de actividades en base a la versión 2.0 de UML.…”

Section: F Valles-barajasunclassified

A Formal Model for the Requirements Diagrams of SysML

Valles-Barajas

2010

IEEE Latin Am. Trans.

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There are several notations to build a model: textual, graphical and mathematical. There are several notations to build a model: textual, graphical and by using mathematics. The Object Management Group (OMG) has developed a graphical notation to model systems called SysML (system modeling language); this notation includes the modeling of the system requirements. In this paper a precise model of the requirements diagrams of SysML is presented. This model is made using a modeling language called Alloy, which has been used to formally specify UML diagrams.

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On the Meaning of SysML Activity Diagrams

Abstract: In this paper, we aim to ascribe a meaning to SysML activity diagrams. To

Cited by 16 publications

References 19 publications

Formal verification of components assembly based on SysML and interface automata

Formal verification of components assembly based on SysML and interface automata

An approach: SysML-based automated requirements verification

A Formal Model for the Requirements Diagrams of SysML

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