Spin-based memory and logic devices are the subject of an intense research activity motivated by the perspective to overcome power, performance and architectural bottlenecks of CMOS-based devices. Among potential material candidates in this field, graphene (Gr) carries great expectations because of its unique electronic transport properties. So far, graphene has been employed mainly in "lateral" spintronic devices, where ferromagnetic electrodes are deposited on top of graphene and electron current flows in the plane of the carbon sheet [1,2,3]. In such devices, oxide tunnel barriers (MgO or Al 2 O 3 ) are often inserted between graphene and the ferromagnetic metals to overcome the conductance mismatch problem [4,5], allowing spin-polarized electrons to be efficiently injected into or extracted