On the multiple shared memory module approach to ATM switching

Wei, Sherry; Kumar, Vijay

doi:10.1109/infcom.1992.263575

Cited by 17 publications

(3 citation statements)

References 12 publications

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“…A similar property is derived in [14] for an optimal switch with no reference to a specific architecture.…”

Section: Architecturementioning

confidence: 89%

“…Such a structure can be viewed as a queueing system where each output port is a server and the cells destined for that output port are the customers for that server. Following [14], we say that a switch architecture is optimal if its underlying queuing system has the best delay-throughput performance. In such an architecture (or queuing system) the only delay that a cell experiences is the delay of the queue of its output port.…”

Section: Multiple Shared Memory Switchmentioning

confidence: 99%

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A multiple shared memory switch

Naraghi-Pour

Hegde

Reddy

Proceedings of 28th Southeastern Symposium on System Theory

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One of the problems that shared memory switche,s have is that in order to build large switches the memory access requirements become stringent. One way to overcome this is to utilize multiple buflers which space division multiplex the input lines and thereby alleviate the memory access requirements. However, previous attempts to implement multibuffered shared memory switches have suffered from serious limitations. We describe in this work a multibuffered architecture that oflers tremendous potential. It is able to fully share the buffer, it guarantees the minimum delay switching of all cells, it can accomplish multicast and multi-channel switching, it can accommodate various priorities and classes of trafic while maintaining high performance o n account of very eficient buffer utilization.

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“…A similar property is derived in [14] for an optimal switch with no reference to a specific architecture.…”

Section: Architecturementioning

confidence: 89%

Section: Multiple Shared Memory Switchmentioning

confidence: 99%

A multiple shared memory switch

Naraghi-Pour

Hegde

Reddy

Proceedings of 28th Southeastern Symposium on System Theory

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show abstract

“…Because of this optimality, and the great expense of optical memory, shared memory architectures are commonly used in studies of optical switches [2] - [4]. The performance of an optical switch architecture is typically obtained by computer simulation, and the results are approximate.…”

mentioning

confidence: 99%

An analysis tool for predicting performance in an all-optical time division multiplexing data switch

Bergstrom

Vernon²,

Ingram³

et al.

Proceedings of ICC'97 - International Conference on Communications

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Performance of shared memory architectures for optical switching is typically obtained by simulation, and in low packet loss regions is subject to statistical error or excessive computer run times. To obtain a reliable measure of performance, a Markov chain with a small number of states has been developed to model the switch's behavior. This reduced chain E s derived from a full Markov chain which more directly models the switch. Equations to count the number of states for both Markov chains are derived. Packet loss results derived from the reduced Markov chain are compared with simulation results.Research has shown that the shared memory architecture, shown in Figure 1, is optimal for optical switches in regard to minimizing the amount of memory required to achieve a particular packet loss rate [l]. Because of this optimality, and the great expense of optical memory, shared memory architectures are commonly used in studies of optical switches [2] - [4]. The performance of an optical switch architecture is typically obtained by computer simulation, and the results are approximate. When obtaining packet loss rates on the order of via computer simulation, the simulations can take an excessive amount of time to run in order to generate statistically accurate results. To avoid the long run times, we considered a Markov chain model for the switch of Figure 1, assuming uniform traffic. However, as we show in this paper, the number of states in the Markov chain can be tens or hundereds of thousands for reasonably sized switches. Just computing the transition matrix for such a large number of states can be prohibitive. As an alternative, we present a reduced Markov description that yields transition matrices that can be generated in a timely fashion on an average comFigure 1: Shared Memory Switch Architecture puter workstation. DevelopmentIn developing a Markov chain with a relativelj. small number of states, a much larger Markov chain was first developed because it more directly models the switch's behavior. We shall call this larger Markov chain the "full" state description Markov chain. The full state description is a vector of numbers, N + 1 long, where N represents the number of external data ports on the switch. The first N numbers of this vector correspond to the N possible packet groups in memory, where a group is defined as the packets in memory destined for the same output port. The ith element of this vector, i 5 N , is the number of packets in memory destined for the ith output port. The sum of these N elements must be less than or equal to M , the number of memory cells of the switch. The N + 1st number represents the sum of all packets at the output ports in the process 0-7803-3925-8/97 $1 0.00 0 1 997 IEEE 1325

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Review of recent shared memory based ATM switches

Sharma

1999

Computer Communications

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On the multiple shared memory module approach to ATM switching

Cited by 17 publications

References 12 publications

A multiple shared memory switch

A multiple shared memory switch

An analysis tool for predicting performance in an all-optical time division multiplexing data switch

Review of recent shared memory based ATM switches

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