On the performance and energy efficiency of FPGAs and GPUs for polyphase channelization

Adhinarayanan, Vignesh; Koehn, Thaddeus; Kȩpa, Krzysztof; Feng, Wu-chun; Athanas, Peter

doi:10.1109/reconfig.2014.7032542

Cited by 9 publications

(3 citation statements)

References 18 publications

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“…Additionally, [33] characterized the performance of GPGPUs, when employed for three different operations, namely Fast Fourier Transform (FFT), Quadrature Phase Shift Keying (QPSK) demapper and Infinite Impulse Response (IIR) filter. Similarly, [41] compared the processing throughput and energy efficiency of a particular FPGA and a particular GPGPU, when implementing both the FFT and a Finite Impulse Response (FIR) filter.…”

Section: Gpu Computing and Implementationsmentioning

confidence: 99%

Implementation of a Fully-Parallel Turbo Decoder on a General-Purpose Graphics Processing Unit

et al. 2016

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Turbo codes comprising a parallel concatenation of upper and lower convolutional codes are widely employed in the state-of-the-art wireless communication standards, since they facilitate transmission throughputs that closely approach the channel capacity. However, this necessitates high processing throughputs in order for the turbo code to support real-time communications. In the state-of-the-art turbo code implementations, the processing throughput is typically limited by the data dependences that occur within the forward and backward recursions of the Log-BCJR algorithm, which is employed during turbo decoding. In contrast to the highly serial Log-BCJR turbo decoder, we have recently proposed a novel fully parallel turbo decoder (FPTD) algorithm, which can eliminate the data dependences and perform fully parallel processing. In this paper, we propose an optimized FPTD algorithm, which reformulates the operation of the FPTD algorithm so that the upper and lower decoders have identical operation, in order to support single instruction multiple data operation. This allows us to develop a novel general purpose graphics processing unit (GPGPU) implementation of the FPTD, which has application in software-defined radios and virtualized cloud-radio access networks. As a benefit of its higher degree of parallelism, we show that our FPTD improves the higher processing throughput of the Log-BCJR turbo decoder by between 2.3 and 9.2 times, when employing a high-specification GPGPU. However, this is achieved at the cost of a moderate increase of the overall complexity by between 1.7 and 3.3 times.INDEX TERMS Fully-parallel turbo decoder, parallel processing, GPGPU computing, software defined radio, could radio access network.

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Section: Gpu Computing and Implementationsmentioning

confidence: 99%

Implementation of a Fully-Parallel Turbo Decoder on a General-Purpose Graphics Processing Unit

et al. 2016

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“…By measuring the alignment of the input samples, we can select the correctly aligned taps. For example, if the input register is aligned with two floats, GR will choose to multiply with d taps [2] (a set of taps aligned with two floats). $ indicates unaligned data and x[0], .., x [9] are the input samples.…”

Section: Polyphase Filterbank Channelizermentioning

confidence: 99%

“…While FPGA-based approaches can provide the required processing performance, they lack the run-time flexibility of GPPbased approaches [5]. The authors in [1,2,8,14] show the possibility to perform a PFB channelizer with a GPU underlying processing unit. However, these solutions are (i) not implemented as GR modules, (ii) not provided as an open-source and (iii) not optimized with respect to throughput and latency for data transfer between system memory (RAM) and GPU memory.…”

Section: Introductionmentioning

confidence: 99%

High-Performance Wideband SDR Channelizers

Alyafawi

Durand

Braun

2016

Lecture Notes in Computer Science

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The essential process to analyze signals from multicarrier communication systems is to isolate independent communication channels using a channelizer. To implement a channelizer in software-defined radio systems, the Polyphase Filterbank (PFB) is commonly used. For real-time applications, the PFB has to process the digitized signal faster or equal to its sampling rate. Depending on the underlying hardware, PFB can run on a CPU, a Graphical Processing Unit (GPU), or even a Field-Programmable Gate Arrays (FPGA). CPUs and GPUs are more reconfigurable and scalable platforms than FPGAs. In this paper, we optimize an existing implementation of a CPU-based channelizer and implement a novel GPU-based channelizer. Our proposed solutions deliver an overall improvement of 30% for the CPU optimization on Intel Core i7-4790 @ 3.60 GHz, and a 3.2-fold improvement for the GPU implementation on AMD R9 290, when compared to the original CPU-based implementation.

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Implementation of a Multirate Resampler for Multi-carrier Systems on GPUs

Kim

Bhattacharyya

2017

J Sign Process Syst

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On the performance and energy efficiency of FPGAs and GPUs for polyphase channelization

Cited by 9 publications

References 18 publications

Implementation of a Fully-Parallel Turbo Decoder on a General-Purpose Graphics Processing Unit

Implementation of a Fully-Parallel Turbo Decoder on a General-Purpose Graphics Processing Unit

High-Performance Wideband SDR Channelizers

Implementation of a Multirate Resampler for Multi-carrier Systems on GPUs

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